kopia lustrzana https://github.com/espressif/esp-idf
140 wiersze
4.1 KiB
C
140 wiersze
4.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "esp_err.h"
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#include "lp_core_uart.h"
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#include "driver/rtc_io.h"
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#include "soc/lp_uart_struct.h"
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#include "hal/uart_hal.h"
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#include "hal/rtc_io_types.h"
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#include "esp_clk_tree.h"
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#include "esp_private/periph_ctrl.h"
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#define LP_UART_PORT_NUM LP_UART_NUM_0
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#define LP_UART_TX_IDLE_NUM_DEFAULT (0U)
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/* LP UART HAL Context */
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uart_hal_context_t hal = {
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.dev = (uart_dev_t *)UART_LL_GET_HW(LP_UART_NUM_0),
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};
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static esp_err_t lp_core_uart_param_config(const lp_core_uart_cfg_t *cfg)
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{
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esp_err_t ret = ESP_OK;
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/* Argument sanity check */
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if ((cfg->uart_proto_cfg.rx_flow_ctrl_thresh > SOC_LP_UART_FIFO_LEN) ||
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(cfg->uart_proto_cfg.flow_ctrl > UART_HW_FLOWCTRL_MAX) ||
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(cfg->uart_proto_cfg.data_bits > UART_DATA_BITS_MAX)) {
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// Invalid config
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return ESP_ERR_INVALID_ARG;
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}
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/* Initialize LP UART HAL with default parameters */
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uart_hal_init(&hal, LP_UART_PORT_NUM);
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/* Get LP UART source clock frequency */
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uint32_t sclk_freq = 0;
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soc_periph_lp_uart_clk_src_t clk_src = cfg->lp_uart_source_clk ? cfg->lp_uart_source_clk : LP_UART_SCLK_DEFAULT;
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ret = esp_clk_tree_src_get_freq_hz((soc_module_clk_t)clk_src, ESP_CLK_TREE_SRC_FREQ_PRECISION_CACHED, &sclk_freq);
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if (ret != ESP_OK) {
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// Unable to fetch LP UART source clock frequency
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return ESP_FAIL;
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}
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// LP UART clock source is mixed with other peripherals in the same register
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PERIPH_RCC_ATOMIC() {
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lp_uart_ll_set_source_clk(hal.dev, clk_src);
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}
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/* Override protocol parameters from the configuration */
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uart_hal_set_baudrate(&hal, cfg->uart_proto_cfg.baud_rate, sclk_freq);
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uart_hal_set_parity(&hal, cfg->uart_proto_cfg.parity);
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uart_hal_set_data_bit_num(&hal, cfg->uart_proto_cfg.data_bits);
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uart_hal_set_stop_bits(&hal, cfg->uart_proto_cfg.stop_bits);
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uart_hal_set_tx_idle_num(&hal, LP_UART_TX_IDLE_NUM_DEFAULT);
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uart_hal_set_hw_flow_ctrl(&hal, cfg->uart_proto_cfg.flow_ctrl, cfg->uart_proto_cfg.rx_flow_ctrl_thresh);
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/* Reset Tx/Rx FIFOs */
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uart_hal_rxfifo_rst(&hal);
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uart_hal_txfifo_rst(&hal);
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return ret;
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}
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static esp_err_t lp_uart_config_io(gpio_num_t pin, rtc_gpio_mode_t direction)
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{
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/* Initialize LP_IO */
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esp_err_t ret = rtc_gpio_init(pin);
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if (ret != ESP_OK) {
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return ESP_FAIL;
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}
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/* Set LP_IO direction */
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ret = rtc_gpio_set_direction(pin, direction);
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if (ret != ESP_OK) {
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return ESP_FAIL;
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}
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/* Set LP_IO function */
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ret = rtc_gpio_iomux_func_sel(pin, 1);
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return ret;
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}
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static esp_err_t lp_core_uart_set_pin(const lp_core_uart_cfg_t *cfg)
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{
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esp_err_t ret = ESP_OK;
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/* Argument sanity check */
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if ((cfg->uart_pin_cfg.tx_io_num != GPIO_NUM_5) ||
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(cfg->uart_pin_cfg.rx_io_num != GPIO_NUM_4) ||
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(cfg->uart_pin_cfg.rts_io_num != GPIO_NUM_2) ||
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(cfg->uart_pin_cfg.cts_io_num != GPIO_NUM_3)) {
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// Invalid IO config
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return ESP_ERR_INVALID_ARG;
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}
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/* Configure Tx Pin */
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ret = lp_uart_config_io(cfg->uart_pin_cfg.tx_io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
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/* Configure Rx Pin */
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ret = lp_uart_config_io(cfg->uart_pin_cfg.rx_io_num, RTC_GPIO_MODE_INPUT_ONLY);
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/* Configure RTS Pin */
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ret = lp_uart_config_io(cfg->uart_pin_cfg.rts_io_num, RTC_GPIO_MODE_OUTPUT_ONLY);
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/* Configure CTS Pin */
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ret = lp_uart_config_io(cfg->uart_pin_cfg.cts_io_num, RTC_GPIO_MODE_INPUT_ONLY);
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return ret;
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}
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esp_err_t lp_core_uart_init(const lp_core_uart_cfg_t *cfg)
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{
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esp_err_t ret = ESP_OK;
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/* Argument sanity check */
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if (!cfg) {
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// NULL configuration
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return ESP_ERR_INVALID_ARG;
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}
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/* Configure LP UART protocol parameters */
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ret = lp_core_uart_param_config(cfg);
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if (ret != ESP_OK) {
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// Invalid protocol configuration
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return ESP_FAIL;
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}
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/* Configure LP UART IO pins */
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ret = lp_core_uart_set_pin(cfg);
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if (ret != ESP_OK) {
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// Invalid IO configuration
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return ESP_FAIL;
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}
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return ret;
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}
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