kopia lustrzana https://github.com/espressif/esp-idf
204 wiersze
6.4 KiB
C
204 wiersze
6.4 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <stdbool.h>
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#include "hal/wdt_types.h"
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#include "hal/wdt_hal.h"
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/* ---------------------------- Init and Config ----------------------------- */
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void wdt_hal_init(wdt_hal_context_t *hal, wdt_inst_t wdt_inst, uint32_t prescaler, bool enable_intr)
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{
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//Initialize HAL context
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memset(hal, 0, sizeof(wdt_hal_context_t));
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if (wdt_inst == WDT_MWDT0) {
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hal->mwdt_dev = &TIMERG0;
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}
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#if SOC_TIMER_GROUPS >= 2
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else if (wdt_inst == WDT_MWDT1) {
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hal->mwdt_dev = &TIMERG1;
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}
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#endif
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else {
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#if CONFIG_IDF_TARGET_ESP32C6 || CONFIG_IDF_TARGET_ESP32H2 // ESP32C6-TODO, ESP32H2-TODO: IDF-5653
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hal->rwdt_dev = &LP_WDT;
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#else
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hal->rwdt_dev = &RTCCNTL;
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#endif
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}
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hal->inst = wdt_inst;
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if (hal->inst == WDT_RWDT) {
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//Unlock RTC WDT
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rwdt_ll_write_protect_disable(hal->rwdt_dev);
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//Disable RTC WDT, all stages, and all interrupts.
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rwdt_ll_disable(hal->rwdt_dev);
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rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE0);
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rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE1);
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rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE2);
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rwdt_ll_disable_stage(hal->rwdt_dev, WDT_STAGE3);
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#ifdef CONFIG_IDF_TARGET_ESP32
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//Enable or disable level interrupt. Edge interrupt is always disabled.
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rwdt_ll_set_edge_intr(hal->rwdt_dev, false);
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rwdt_ll_set_level_intr(hal->rwdt_dev, enable_intr);
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#else
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//Enable or disable chip reset on timeout, and length of chip reset signal
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rwdt_ll_set_chip_reset_width(hal->rwdt_dev, 0);
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rwdt_ll_set_chip_reset_en(hal->rwdt_dev, false);
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#endif
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rwdt_ll_clear_intr_status(hal->rwdt_dev);
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rwdt_ll_set_intr_enable(hal->rwdt_dev, enable_intr);
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//Set default values
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#if SOC_CPU_CORES_NUM > 1
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rwdt_ll_set_appcpu_reset_en(hal->rwdt_dev, true);
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#endif
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rwdt_ll_set_procpu_reset_en(hal->rwdt_dev, true);
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rwdt_ll_set_pause_in_sleep_en(hal->rwdt_dev, true);
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rwdt_ll_set_cpu_reset_length(hal->rwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
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rwdt_ll_set_sys_reset_length(hal->rwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
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//Lock RTC WDT
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rwdt_ll_write_protect_enable(hal->rwdt_dev);
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} else {
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//Unlock WDT
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mwdt_ll_write_protect_disable(hal->mwdt_dev);
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//Disable WDT and stages.
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mwdt_ll_disable(hal->mwdt_dev);
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mwdt_ll_disable_stage(hal->mwdt_dev, 0);
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mwdt_ll_disable_stage(hal->mwdt_dev, 1);
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mwdt_ll_disable_stage(hal->mwdt_dev, 2);
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mwdt_ll_disable_stage(hal->mwdt_dev, 3);
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#if CONFIG_IDF_TARGET_ESP32 || CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3
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//Enable or disable level interrupt. Edge interrupt is always disabled.
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mwdt_ll_set_edge_intr(hal->mwdt_dev, false);
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mwdt_ll_set_level_intr(hal->mwdt_dev, enable_intr);
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#endif
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mwdt_ll_clear_intr_status(hal->mwdt_dev);
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mwdt_ll_set_intr_enable(hal->mwdt_dev, enable_intr);
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//Set default values
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mwdt_ll_set_cpu_reset_length(hal->mwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
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mwdt_ll_set_sys_reset_length(hal->mwdt_dev, WDT_RESET_SIG_LENGTH_3_2us);
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//Set tick period
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mwdt_ll_set_prescaler(hal->mwdt_dev, prescaler);
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//Lock WDT
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mwdt_ll_write_protect_enable(hal->mwdt_dev);
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}
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}
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void wdt_hal_deinit(wdt_hal_context_t *hal)
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{
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if (hal->inst == WDT_RWDT) {
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//Unlock WDT
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rwdt_ll_write_protect_disable(hal->rwdt_dev);
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//Disable WDT and clear any interrupts
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rwdt_ll_feed(hal->rwdt_dev);
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rwdt_ll_disable(hal->rwdt_dev);
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rwdt_ll_clear_intr_status(hal->rwdt_dev);
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rwdt_ll_set_intr_enable(hal->rwdt_dev, false);
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//Lock WDT
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rwdt_ll_write_protect_enable(hal->rwdt_dev);
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} else {
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//Unlock WDT
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mwdt_ll_write_protect_disable(hal->mwdt_dev);
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//Disable WDT and clear/disable any interrupts
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mwdt_ll_feed(hal->mwdt_dev);
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mwdt_ll_disable(hal->mwdt_dev);
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mwdt_ll_clear_intr_status(hal->mwdt_dev);
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mwdt_ll_set_intr_enable(hal->mwdt_dev, false);
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//Lock WDT
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mwdt_ll_write_protect_enable(hal->mwdt_dev);
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}
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//Deinit HAL context
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hal->mwdt_dev = NULL;
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}
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void wdt_hal_config_stage(wdt_hal_context_t *hal, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
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{
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if (hal->inst == WDT_RWDT) {
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rwdt_ll_config_stage(hal->rwdt_dev, stage, timeout_ticks, behavior);
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} else {
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mwdt_ll_config_stage(hal->mwdt_dev, stage, timeout_ticks, behavior);
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}
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}
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/* -------------------------------- Runtime --------------------------------- */
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void wdt_hal_write_protect_disable(wdt_hal_context_t *hal)
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{
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if (hal->inst == WDT_RWDT) {
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rwdt_ll_write_protect_disable(hal->rwdt_dev);
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} else {
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mwdt_ll_write_protect_disable(hal->mwdt_dev);
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}
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}
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void wdt_hal_write_protect_enable(wdt_hal_context_t *hal)
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{
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if (hal->inst == WDT_RWDT) {
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rwdt_ll_write_protect_enable(hal->rwdt_dev);
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} else {
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mwdt_ll_write_protect_enable(hal->mwdt_dev);
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}
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}
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void wdt_hal_enable(wdt_hal_context_t *hal)
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{
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if (hal->inst == WDT_RWDT) {
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rwdt_ll_feed(hal->rwdt_dev);
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rwdt_ll_enable(hal->rwdt_dev);
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} else {
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mwdt_ll_feed(hal->mwdt_dev);
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mwdt_ll_enable(hal->mwdt_dev);
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}
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}
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void wdt_hal_disable(wdt_hal_context_t *hal)
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{
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if (hal->inst == WDT_RWDT) {
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rwdt_ll_disable(hal->rwdt_dev);
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} else {
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mwdt_ll_disable(hal->mwdt_dev);
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}
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}
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void wdt_hal_handle_intr(wdt_hal_context_t *hal)
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{
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if (hal->inst == WDT_RWDT) {
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rwdt_ll_feed(hal->rwdt_dev);
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rwdt_ll_clear_intr_status(hal->rwdt_dev);
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} else {
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mwdt_ll_feed(hal->mwdt_dev);
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mwdt_ll_clear_intr_status(hal->mwdt_dev);
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}
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}
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void wdt_hal_feed(wdt_hal_context_t *hal)
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{
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if (hal->inst == WDT_RWDT) {
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rwdt_ll_feed(hal->rwdt_dev);
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} else {
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mwdt_ll_feed(hal->mwdt_dev);
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}
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}
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void wdt_hal_set_flashboot_en(wdt_hal_context_t *hal, bool enable)
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{
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if (hal->inst == WDT_RWDT) {
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rwdt_ll_set_flashboot_en(hal->rwdt_dev, enable);
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} else {
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mwdt_ll_set_flashboot_en(hal->mwdt_dev, enable);
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}
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}
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bool wdt_hal_is_enabled(wdt_hal_context_t *hal)
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{
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if (hal->inst == WDT_RWDT) {
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return rwdt_ll_check_if_enabled(hal->rwdt_dev);
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} else {
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return mwdt_ll_check_if_enabled(hal->mwdt_dev);
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}
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}
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