kopia lustrzana https://github.com/espressif/esp-idf
099f648686
This commit fixes an issue where in the ULP RISC-V I2C example causes a spurious wakeup of the main CPU because of a Trap signal when the ULP core does not meet the wakeup threshold values. This was due to the fact that the RTC_CNTL_COCPU_DONE signal was being set before the RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V core to not reset properly on each cycle. Closes https://github.com/espressif/esp-idf/issues/10301 |
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| .. | ||
| adc | ||
| ds18b20_onewire | ||
| gpio | ||
| gpio_interrupt | ||
| i2c | ||
| uart_print | ||