kopia lustrzana https://github.com/espressif/esp-idf
62 wiersze
1.6 KiB
ArmAsm
62 wiersze
1.6 KiB
ArmAsm
/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <xtensa/coreasm.h>
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#include <xtensa/corebits.h>
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#include <xtensa/config/system.h>
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#include <xtensa/hal.h>
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/* esp_test_ipc_isr_asm(void *arg)
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*
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* It should be called by the CALLX0 command from the handler of High-priority interrupt.
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* Only these registers [a2, a3, a4] can be used here.
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*/
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.section .iram1, "ax"
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.align 4
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.global esp_test_ipc_isr_asm
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.type esp_test_ipc_isr_asm, @function
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// Args:
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// a2 - void* arg
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esp_test_ipc_isr_asm:
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movi a3, 0xa5a5
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s32i a3, a2, 0
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ret
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/* esp_test_ipc_isr_get_other_core_id(void *arg)
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*
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* this function puts the core_id of the other CPU in the arg.
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* use only a2, a3 and a4 regs here.
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*/
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.section .iram1, "ax"
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.align 4
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.global esp_test_ipc_isr_get_other_core_id
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.type esp_test_ipc_isr_get_other_core_id, @function
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// Args:
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// a2 - void* arg
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esp_test_ipc_isr_get_other_core_id:
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rsr.prid a3
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extui a3, a3, 13, 1
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s32i a3, a2, 0
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ret
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/* esp_test_ipc_isr_get_cycle_count_other_cpu(void *arg)
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*
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* this function puts CCOUNT of the other CPU in the arg.
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* use only a2, a3 and a4 regs here.
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*/
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.section .iram1, "ax"
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.align 4
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.global esp_test_ipc_isr_get_cycle_count_other_cpu
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.type esp_test_ipc_isr_get_cycle_count_other_cpu, @function
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// Args:
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// a2 - void* arg
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esp_test_ipc_isr_get_cycle_count_other_cpu:
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rsr.ccount a3
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s32i a3, a2, 0
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ret
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