kopia lustrzana https://github.com/espressif/esp-idf
387 wiersze
13 KiB
C
387 wiersze
13 KiB
C
/*
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* SPDX-FileCopyrightText: 2010-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// Test for spi_flash_{read,write}.
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#include <assert.h>
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#include <stdint.h>
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#include <stdio.h>
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#include <string.h>
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#include <sys/param.h>
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#include "unity.h"
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#include "spi_flash_mmap.h"
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#include "esp_private/cache_utils.h"
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#include "soc/timer_periph.h"
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#include "esp_attr.h"
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#include "esp_heap_caps.h"
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#include "esp_rom_spiflash.h"
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#include "esp_flash.h"
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#include "esp_partition.h"
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#if CONFIG_IDF_TARGET_ESP32
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// Used for rom_fix function
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#include "esp32/rom/spi_flash.h"
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#endif
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extern const esp_partition_t *get_test_data_partition(void);
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#define MIN_BLOCK_SIZE 12
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/* Base offset in flash for tests. */
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static size_t start;
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static void setup_tests(void)
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{
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if (start == 0) {
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const esp_partition_t *part = get_test_data_partition();
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start = part->address;
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printf("Test data partition @ 0x%x\n", start);
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}
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}
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#ifndef CONFIG_SPI_FLASH_MINIMAL_TEST
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#define CONFIG_SPI_FLASH_MINIMAL_TEST 1
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#endif
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static void fill(char *dest, int32_t start, int32_t len)
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{
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for (int32_t i = 0; i < len; i++) {
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*(dest + i) = (char) (start + i);
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}
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}
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static int cmp_or_dump(const void *a, const void *b, size_t len)
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{
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int r = memcmp(a, b, len);
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if (r != 0) {
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for (int i = 0; i < len; i++) {
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fprintf(stderr, "%02x", ((unsigned char *) a)[i]);
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}
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fprintf(stderr, "\n");
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for (int i = 0; i < len; i++) {
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fprintf(stderr, "%02x", ((unsigned char *) b)[i]);
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}
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fprintf(stderr, "\n");
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}
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return r;
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}
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static void IRAM_ATTR test_read(int src_off, int dst_off, int len)
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{
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uint32_t src_buf[16];
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char dst_buf[64], dst_gold[64];
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fprintf(stderr, "src=%d dst=%d len=%d\n", src_off, dst_off, len);
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memset(src_buf, 0xAA, sizeof(src_buf));
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fill(((char *) src_buf) + src_off, src_off, len);
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ESP_ERROR_CHECK(esp_flash_erase_region(NULL, (start + src_off) & ~(0x10000 - 1), SPI_FLASH_SEC_SIZE));
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spi_flash_disable_interrupts_caches_and_other_cpu();
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esp_rom_spiflash_result_t rc = esp_rom_spiflash_write(start, src_buf, sizeof(src_buf));
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spi_flash_enable_interrupts_caches_and_other_cpu();
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TEST_ASSERT_EQUAL_HEX(rc, ESP_ROM_SPIFLASH_RESULT_OK);
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memset(dst_buf, 0x55, sizeof(dst_buf));
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memset(dst_gold, 0x55, sizeof(dst_gold));
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fill(dst_gold + dst_off, src_off, len);
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ESP_ERROR_CHECK(esp_flash_read(NULL, dst_buf + dst_off, start + src_off, len));
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TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0);
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}
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TEST_CASE("Test spi_flash_read", "[spi_flash][esp_flash]")
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{
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setup_tests();
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#if CONFIG_SPI_FLASH_MINIMAL_TEST
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test_read(0, 0, 0);
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test_read(0, 0, 4);
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test_read(0, 0, 16);
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test_read(0, 0, 64);
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test_read(0, 0, 1);
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test_read(0, 1, 1);
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test_read(1, 0, 1);
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test_read(1, 1, 1);
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test_read(1, 1, 2);
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test_read(1, 1, 3);
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test_read(1, 1, 4);
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test_read(1, 1, 5);
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test_read(3, 2, 5);
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test_read(0, 0, 17);
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test_read(0, 1, 17);
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test_read(1, 0, 17);
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test_read(1, 1, 17);
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test_read(1, 1, 18);
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test_read(1, 1, 19);
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test_read(1, 1, 20);
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test_read(1, 1, 21);
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test_read(3, 2, 21);
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test_read(4, 4, 60);
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test_read(59, 0, 5);
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test_read(60, 0, 4);
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test_read(60, 0, 3);
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test_read(60, 0, 2);
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test_read(63, 0, 1);
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test_read(64, 0, 0);
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test_read(59, 59, 5);
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test_read(60, 60, 4);
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test_read(60, 60, 3);
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test_read(60, 60, 2);
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test_read(63, 63, 1);
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test_read(64, 64, 0);
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#else
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/* This will run a more thorough test but will slam flash pretty hard. */
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for (int src_off = 1; src_off < 16; src_off++) {
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for (int dst_off = 0; dst_off < 16; dst_off++) {
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for (int len = 0; len < 32; len++) {
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test_read(dst_off, src_off, len);
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}
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}
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}
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#endif
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}
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extern void spi_common_set_dummy_output(esp_rom_spiflash_read_mode_t mode);
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extern void spi_dummy_len_fix(uint8_t spi, uint8_t freqdiv);
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static void IRAM_ATTR fix_rom_func(void)
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{
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uint32_t freqdiv = 0;
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#if CONFIG_ESPTOOLPY_FLASHFREQ_80M && !CONFIG_ESPTOOLPY_OCT_FLASH
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freqdiv = 1;
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_80M && CONFIG_ESPTOOLPY_OCT_FLASH
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freqdiv = 2;
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
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freqdiv = 2;
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_26M
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freqdiv = 3;
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_20M
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freqdiv = 4;
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_120M
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freqdiv = 2;
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#endif
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#if CONFIG_IDF_TARGET_ESP32
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uint32_t dummy_bit = 0;
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#if CONFIG_ESPTOOLPY_FLASHFREQ_80M
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dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_80M;
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_40M
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dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_40M;
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_26M
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dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_26M;
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_20M
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dummy_bit = ESP_ROM_SPIFLASH_DUMMY_LEN_PLUS_20M;
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#endif
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g_rom_spiflash_dummy_len_plus[1] = dummy_bit;
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#else
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spi_dummy_len_fix(1, freqdiv);
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#endif//CONFIG_IDF_TARGET_ESP32
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esp_rom_spiflash_read_mode_t read_mode;
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#if CONFIG_ESPTOOLPY_FLASHMODE_QIO
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read_mode = ESP_ROM_SPIFLASH_QIO_MODE;
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#elif CONFIG_ESPTOOLPY_FLASHMODE_QOUT
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read_mode = ESP_ROM_SPIFLASH_QOUT_MODE;
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#elif CONFIG_ESPTOOLPY_FLASHMODE_DIO
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read_mode = ESP_ROM_SPIFLASH_DIO_MODE;
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#elif CONFIG_ESPTOOLPY_FLASHMODE_DOUT
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read_mode = ESP_ROM_SPIFLASH_DOUT_MODE;
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#elif CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_STR
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read_mode = ESP_ROM_SPIFLASH_OPI_STR_MODE;
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#elif CONFIG_ESPTOOLPY_FLASH_SAMPLE_MODE_DTR
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read_mode = ESP_ROM_SPIFLASH_OPI_DTR_MODE;
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#endif
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#if !CONFIG_IDF_TARGET_ESP32S2 && !CONFIG_IDF_TARGET_ESP32
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spi_common_set_dummy_output(read_mode);
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#endif //!CONFIG_IDF_TARGET_ESP32S2
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esp_rom_spiflash_config_clk(freqdiv, 1);
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#if !CONFIG_ESPTOOLPY_OCT_FLASH
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esp_rom_spiflash_config_readmode(read_mode);
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#endif
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}
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static void IRAM_ATTR test_write(int dst_off, int src_off, int len)
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{
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char src_buf[64], dst_gold[64];
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uint32_t dst_buf[16];
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fprintf(stderr, "dst=%d src=%d len=%d\n", dst_off, src_off, len);
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memset(src_buf, 0x55, sizeof(src_buf));
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fill(src_buf + src_off, src_off, len);
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// Fills with 0xff
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ESP_ERROR_CHECK(esp_flash_erase_region(NULL, (start + src_off) & ~(0x10000 - 1), SPI_FLASH_SEC_SIZE));
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memset(dst_gold, 0xff, sizeof(dst_gold));
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if (len > 0) {
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int pad_left_off = (dst_off & ~3U);
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memset(dst_gold + pad_left_off, 0xff, 4);
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if (dst_off + len > pad_left_off + 4 && (dst_off + len) % 4 != 0) {
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int pad_right_off = ((dst_off + len) & ~3U);
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memset(dst_gold + pad_right_off, 0xff, 4);
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}
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fill(dst_gold + dst_off, src_off, len);
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}
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ESP_ERROR_CHECK(esp_flash_write(NULL, src_buf + src_off, start + dst_off, len));
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fix_rom_func();
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spi_flash_disable_interrupts_caches_and_other_cpu();
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esp_rom_spiflash_result_t rc = esp_rom_spiflash_read(start, dst_buf, sizeof(dst_buf));
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spi_flash_enable_interrupts_caches_and_other_cpu();
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TEST_ASSERT_EQUAL_HEX(rc, ESP_ROM_SPIFLASH_RESULT_OK);
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TEST_ASSERT_EQUAL_INT(cmp_or_dump(dst_buf, dst_gold, sizeof(dst_buf)), 0);
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}
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TEST_CASE("Test esp_flash_write", "[spi_flash][esp_flash]")
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{
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setup_tests();
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#if CONFIG_SPI_FLASH_MINIMAL_TEST
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test_write(0, 0, 0);
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test_write(0, 0, 4);
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test_write(0, 0, 16);
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test_write(0, 0, 64);
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test_write(0, 0, 1);
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test_write(0, 1, 1);
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test_write(1, 0, 1);
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test_write(1, 1, 1);
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test_write(1, 1, 2);
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test_write(1, 1, 3);
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test_write(1, 1, 4);
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test_write(1, 1, 5);
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test_write(3, 2, 5);
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test_write(4, 4, 60);
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test_write(59, 0, 5);
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test_write(60, 0, 4);
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test_write(60, 0, 3);
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test_write(60, 0, 2);
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test_write(63, 0, 1);
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test_write(64, 0, 0);
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test_write(59, 59, 5);
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test_write(60, 60, 4);
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test_write(60, 60, 3);
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test_write(60, 60, 2);
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test_write(63, 63, 1);
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test_write(64, 64, 0);
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#else
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/* This will run a more thorough test but will slam flash pretty hard. */
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for (int dst_off = 1; dst_off < 16; dst_off++) {
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for (int src_off = 0; src_off < 16; src_off++) {
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for (int len = 0; len < 16; len++) {
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test_write(dst_off, src_off, len);
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}
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}
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}
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#endif
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/*
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* Test writing from ROM, IRAM and caches. We don't know what exactly will be
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* written, we're testing that there's no crash here.
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*
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* NB: At the moment these only support aligned addresses, because memcpy
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* is not aware of the 32-but load requirements for these regions.
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*/
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#if CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32H2 || CONFIG_IDF_TARGET_ESP32C6
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#define TEST_SOC_IROM_ADDR (SOC_IROM_LOW)
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#define TEST_SOC_CACHE_RAM_BANK0_ADDR (SOC_IRAM_LOW)
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#define TEST_SOC_CACHE_RAM_BANK1_ADDR (SOC_IRAM_LOW + 0x2000)
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#define TEST_SOC_CACHE_RAM_BANK2_ADDR (SOC_IRAM_LOW + 0x4000)
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#define TEST_SOC_CACHE_RAM_BANK3_ADDR (SOC_IRAM_LOW + 0x6000)
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#define TEST_SOC_IRAM_ADDR (SOC_IRAM_LOW + 0x8000)
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#define TEST_SOC_RTC_IRAM_ADDR (SOC_RTC_IRAM_LOW)
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#define TEST_SOC_RTC_DRAM_ADDR (SOC_RTC_DRAM_LOW)
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ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_IROM_ADDR, start, 16));
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ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_IRAM_ADDR, start, 16));
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ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_CACHE_RAM_BANK0_ADDR, start, 16));
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ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_CACHE_RAM_BANK1_ADDR, start, 16));
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ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_CACHE_RAM_BANK2_ADDR, start, 16));
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ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_CACHE_RAM_BANK3_ADDR, start, 16));
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ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_RTC_IRAM_ADDR, start, 16));
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ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) TEST_SOC_RTC_DRAM_ADDR, start, 16));
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#else
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ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) 0x40000000, start, 16));
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ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) 0x40070000, start, 16));
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ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) 0x40078000, start, 16));
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ESP_ERROR_CHECK(esp_flash_write(NULL, (char *) 0x40080000, start, 16));
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#endif
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}
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#ifdef CONFIG_SPIRAM
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TEST_CASE("spi_flash_read can read into buffer in external RAM", "[spi_flash]")
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{
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uint8_t* buf_ext = (uint8_t*) heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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TEST_ASSERT_NOT_NULL(buf_ext);
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uint8_t* buf_int = (uint8_t*) heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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TEST_ASSERT_NOT_NULL(buf_int);
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TEST_ESP_OK(esp_flash_read(NULL, buf_int, 0x1000, SPI_FLASH_SEC_SIZE));
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TEST_ESP_OK(esp_flash_read(NULL, buf_ext, 0x1000, SPI_FLASH_SEC_SIZE));
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TEST_ASSERT_EQUAL(0, memcmp(buf_ext, buf_int, SPI_FLASH_SEC_SIZE));
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free(buf_ext);
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free(buf_int);
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}
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TEST_CASE("esp_flash_write can write from external RAM buffer", "[spi_flash]")
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{
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uint32_t* buf_ext = (uint32_t*) heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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TEST_ASSERT_NOT_NULL(buf_ext);
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srand(0);
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for (size_t i = 0; i < SPI_FLASH_SEC_SIZE / sizeof(uint32_t); i++)
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{
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uint32_t val = rand();
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buf_ext[i] = val;
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}
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uint8_t* buf_int = (uint8_t*) heap_caps_malloc(SPI_FLASH_SEC_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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TEST_ASSERT_NOT_NULL(buf_int);
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/* Write to flash from buf_ext */
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const esp_partition_t *part = get_test_data_partition();
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TEST_ESP_OK(esp_flash_erase_region(NULL, part->address & ~(0x10000 - 1), SPI_FLASH_SEC_SIZE));
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TEST_ESP_OK(esp_flash_write(NULL, buf_ext, part->address, SPI_FLASH_SEC_SIZE));
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/* Read back to buf_int and compare */
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TEST_ESP_OK(esp_flash_read(NULL, buf_int, part->address, SPI_FLASH_SEC_SIZE));
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TEST_ASSERT_EQUAL(0, memcmp(buf_ext, buf_int, SPI_FLASH_SEC_SIZE));
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free(buf_ext);
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free(buf_int);
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}
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TEST_CASE("spi_flash_read less than 16 bytes into buffer in external RAM", "[spi_flash]")
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{
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uint8_t *buf_ext_8 = (uint8_t *) heap_caps_malloc(MIN_BLOCK_SIZE, MALLOC_CAP_SPIRAM | MALLOC_CAP_8BIT);
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TEST_ASSERT_NOT_NULL(buf_ext_8);
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uint8_t *buf_int_8 = (uint8_t *) heap_caps_malloc(MIN_BLOCK_SIZE, MALLOC_CAP_INTERNAL | MALLOC_CAP_8BIT);
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TEST_ASSERT_NOT_NULL(buf_int_8);
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uint8_t data_8[MIN_BLOCK_SIZE];
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for (int i = 0; i < MIN_BLOCK_SIZE; i++) {
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data_8[i] = i;
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}
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const esp_partition_t *part = get_test_data_partition();
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TEST_ESP_OK(esp_flash_erase_region(NULL, part->address & ~(0x10000 - 1), SPI_FLASH_SEC_SIZE));
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TEST_ESP_OK(esp_flash_write(NULL, data_8, part->address, MIN_BLOCK_SIZE));
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TEST_ESP_OK(esp_flash_read(NULL, buf_ext_8, part->address, MIN_BLOCK_SIZE));
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TEST_ESP_OK(esp_flash_read(NULL, buf_int_8, part->address, MIN_BLOCK_SIZE));
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TEST_ASSERT_EQUAL(0, memcmp(buf_ext_8, data_8, MIN_BLOCK_SIZE));
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TEST_ASSERT_EQUAL(0, memcmp(buf_int_8, data_8, MIN_BLOCK_SIZE));
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if (buf_ext_8) {
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free(buf_ext_8);
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buf_ext_8 = NULL;
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}
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if (buf_int_8) {
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free(buf_int_8);
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buf_int_8 = NULL;
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}
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}
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#endif // CONFIG_SPIRAM
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