kopia lustrzana https://github.com/espressif/esp-idf
107 wiersze
3.0 KiB
C
107 wiersze
3.0 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <freertos/FreeRTOS.h>
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#include <freertos/task.h>
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#include <freertos/semphr.h>
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#include <esp_spi_flash.h>
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#include <rom/spi_flash.h>
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#include <rom/cache.h>
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#include <esp_attr.h>
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#include <soc/dport_reg.h>
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static esp_err_t spi_flash_translate_rc(SpiFlashOpResult rc)
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{
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switch (rc) {
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case SPI_FLASH_RESULT_OK:
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return ESP_OK;
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case SPI_FLASH_RESULT_TIMEOUT:
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return ESP_ERR_FLASH_OP_TIMEOUT;
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case SPI_FLASH_RESULT_ERR:
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default:
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return ESP_ERR_FLASH_OP_FAIL;
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}
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}
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extern void Cache_Flush(int);
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static void IRAM_ATTR spi_flash_disable_interrupts_caches_and_app_cpu()
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{
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vTaskSuspendAll();
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// SET_PERI_REG_MASK(APPCPU_CTRL_REG_C, DPORT_APPCPU_RUNSTALL);
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Cache_Read_Disable(0);
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Cache_Read_Disable(1);
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}
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static void IRAM_ATTR spi_flash_enable_interrupts_caches_and_app_cpu()
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{
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Cache_Read_Enable(0);
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Cache_Read_Enable(1);
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// CLEAR_PERI_REG_MASK(APPCPU_CTRL_REG_C, DPORT_APPCPU_RUNSTALL);
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xTaskResumeAll();
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}
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esp_err_t IRAM_ATTR spi_flash_erase_sector(uint16_t sec)
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{
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spi_flash_disable_interrupts_caches_and_app_cpu();
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SpiFlashOpResult rc;
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if (xPortGetCoreID() == 1) {
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rc = SPI_FLASH_RESULT_ERR;
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}
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else {
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rc = SPIUnlock();
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if (rc == SPI_FLASH_RESULT_OK) {
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rc = SPIEraseSector(sec);
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}
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}
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Cache_Flush(0);
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Cache_Flush(1);
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spi_flash_enable_interrupts_caches_and_app_cpu();
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return spi_flash_translate_rc(rc);
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}
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esp_err_t IRAM_ATTR spi_flash_write(uint32_t dest_addr, const uint32_t *src, uint32_t size)
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{
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spi_flash_disable_interrupts_caches_and_app_cpu();
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SpiFlashOpResult rc;
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if (xPortGetCoreID() == 1) {
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rc = SPI_FLASH_RESULT_ERR;
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}
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else {
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rc = SPIUnlock();
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if (rc == SPI_FLASH_RESULT_OK) {
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rc = SPIWrite(dest_addr, src, (int32_t) size);
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}
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}
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Cache_Flush(0);
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Cache_Flush(1);
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spi_flash_enable_interrupts_caches_and_app_cpu();
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return spi_flash_translate_rc(rc);
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}
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esp_err_t IRAM_ATTR spi_flash_read(uint32_t src_addr, uint32_t *dest, uint32_t size)
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{
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spi_flash_disable_interrupts_caches_and_app_cpu();
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SpiFlashOpResult rc;
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if (xPortGetCoreID() == 1) {
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rc = SPI_FLASH_RESULT_ERR;
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}
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else {
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rc = SPIRead(src_addr, dest, (int32_t) size);
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}
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spi_flash_enable_interrupts_caches_and_app_cpu();
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return spi_flash_translate_rc(rc);
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}
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