Omar Chebib b03c8912c7 Xtensa: fix a bug that altered CPU registers in FPU exception handlers ... * Fixes https://github.com/espressif/esp-idf/issues/11690		2023-07-04 02:45:56 +00:00
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baremetal	xtensa: Add bare metal port stub functions for G0 build test	2023-04-18 15:51:38 +08:00
deprecated_include	xtensa: Move Xtensa RTOS porting layer files to xtensa component	2023-04-18 15:28:05 +08:00
esp32	…
esp32s2	…
esp32s3	hal: Route CPU and Interrupt Controller HAL/LL to esp_cpu calls	2022-06-14 14:40:03 +08:00
include	Merge branch 'contrib/github_pr_10895' into 'master'	2023-05-04 10:41:46 +08:00
trax	…
CMakeLists.txt	xtensa: Add bare metal port stub functions for G0 build test	2023-04-18 15:51:38 +08:00
eri.c	…
linker.lf	xtensa: Move Xtensa RTOS porting layer files to xtensa component	2023-04-18 15:28:05 +08:00
project_include.cmake	tools: strip trailing whitespaces/newline from dump_machine	2023-05-30 13:35:10 +02:00
xt_trax.c	…
xtensa_context.S	xtensa: Move Xtensa RTOS porting layer files to xtensa component	2023-04-18 15:28:05 +08:00
xtensa_intr.c	G0: Support Xtensa targets for G0-only compilation	2022-06-20 11:34:20 +00:00
xtensa_intr_asm.S	G0: Support Xtensa targets for G0-only compilation	2022-06-20 11:34:20 +00:00
xtensa_loadstore_handler.S	xtensa: Move Xtensa RTOS porting layer files to xtensa component	2023-04-18 15:28:05 +08:00
xtensa_vectors.S	Xtensa: fix a bug that altered CPU registers in FPU exception handlers	2023-07-04 02:45:56 +00:00