kopia lustrzana https://github.com/espressif/esp-idf
273 wiersze
9.7 KiB
C
273 wiersze
9.7 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include <assert.h>
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#include <freertos/FreeRTOS.h>
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#include <freertos/task.h>
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#include <freertos/semphr.h>
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#include <rom/spi_flash.h>
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#include <rom/cache.h>
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#include <soc/soc.h>
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#include <soc/dport_reg.h>
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#include "sdkconfig.h"
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#include "esp_ipc.h"
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#include "esp_attr.h"
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#include "esp_spi_flash.h"
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/*
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Driver for SPI flash read/write/erase operations
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In order to perform some flash operations, we need to make sure both CPUs
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are not running any code from flash for the duration of the flash operation.
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In a single-core setup this is easy: we disable interrupts/scheduler and do
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the flash operation. In the dual-core setup this is slightly more complicated.
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We need to make sure that the other CPU doesn't run any code from flash.
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When SPI flash API is called on CPU A (can be PRO or APP), we start
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spi_flash_op_block_func function on CPU B using esp_ipc_call API. This API
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wakes up high priority task on CPU B and tells it to execute given function,
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in this case spi_flash_op_block_func. This function disables cache on CPU B and
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signals that cache is disabled by setting s_flash_op_can_start flag.
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Then the task on CPU A disables cache as well, and proceeds to execute flash
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operation.
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While flash operation is running, interrupts can still run on CPU B.
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We assume that all interrupt code is placed into RAM.
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Once flash operation is complete, function on CPU A sets another flag,
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s_flash_op_complete, to let the task on CPU B know that it can re-enable
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cache and release the CPU. Then the function on CPU A re-enables the cache on
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CPU A as well and returns control to the calling code.
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Additionally, all API functions are protected with a mutex (s_flash_op_mutex).
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In a single core environment (CONFIG_FREERTOS_UNICORE enabled), we simply
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disable both caches, no inter-CPU communication takes place.
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*/
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static esp_err_t spi_flash_translate_rc(SpiFlashOpResult rc);
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static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state);
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static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state);
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static uint32_t s_flash_op_cache_state[2];
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#ifndef CONFIG_FREERTOS_UNICORE
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static SemaphoreHandle_t s_flash_op_mutex;
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static bool s_flash_op_can_start = false;
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static bool s_flash_op_complete = false;
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#endif //CONFIG_FREERTOS_UNICORE
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#ifndef CONFIG_FREERTOS_UNICORE
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static void IRAM_ATTR spi_flash_op_block_func(void* arg)
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{
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// Disable scheduler on this CPU
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vTaskSuspendAll();
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uint32_t cpuid = (uint32_t) arg;
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// Disable cache so that flash operation can start
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spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);
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s_flash_op_can_start = true;
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while (!s_flash_op_complete) {
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// until we have a way to use interrupts for inter-CPU communication,
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// busy loop here and wait for the other CPU to finish flash operation
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}
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// Flash operation is complete, re-enable cache
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spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);
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// Re-enable scheduler
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xTaskResumeAll();
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}
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void spi_flash_init()
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{
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s_flash_op_mutex = xSemaphoreCreateMutex();
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}
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static void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
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{
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// Take the API lock
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xSemaphoreTake(s_flash_op_mutex, portMAX_DELAY);
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const uint32_t cpuid = xPortGetCoreID();
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const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
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if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED) {
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// Scheduler hasn't been started yet, it means that spi_flash API is being
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// called from the 2nd stage bootloader or from user_start_cpu0, i.e. from
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// PRO CPU. APP CPU is either in reset or spinning inside user_start_cpu1,
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// which is in IRAM. So it is safe to disable cache for the other_cpuid here.
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assert(other_cpuid == 1);
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spi_flash_disable_cache(other_cpuid, &s_flash_op_cache_state[other_cpuid]);
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} else {
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// Signal to the spi_flash_op_block_task on the other CPU that we need it to
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// disable cache there and block other tasks from executing.
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s_flash_op_can_start = false;
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s_flash_op_complete = false;
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esp_ipc_call(other_cpuid, &spi_flash_op_block_func, (void*) other_cpuid);
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while (!s_flash_op_can_start) {
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// Busy loop and wait for spi_flash_op_block_func to disable cache
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// on the other CPU
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}
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// Disable scheduler on CPU cpuid
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vTaskSuspendAll();
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// This is guaranteed to run on CPU <cpuid> because the other CPU is now
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// occupied by highest priority task
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assert(xPortGetCoreID() == cpuid);
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}
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// Disable cache on this CPU as well
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spi_flash_disable_cache(cpuid, &s_flash_op_cache_state[cpuid]);
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}
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static void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
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{
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const uint32_t cpuid = xPortGetCoreID();
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const uint32_t other_cpuid = (cpuid == 0) ? 1 : 0;
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// Re-enable cache on this CPU
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spi_flash_restore_cache(cpuid, s_flash_op_cache_state[cpuid]);
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if (xTaskGetSchedulerState() == taskSCHEDULER_NOT_STARTED) {
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// Scheduler is not running yet — this means we are running on PRO CPU.
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// other_cpuid is APP CPU, and it is either in reset or is spinning in
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// user_start_cpu1, which is in IRAM. So we can simply reenable cache.
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assert(other_cpuid == 1);
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spi_flash_restore_cache(other_cpuid, s_flash_op_cache_state[other_cpuid]);
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} else {
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// Signal to spi_flash_op_block_task that flash operation is complete
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s_flash_op_complete = true;
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// Resume tasks on the current CPU
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xTaskResumeAll();
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}
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// Release API lock
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xSemaphoreGive(s_flash_op_mutex);
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}
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#else // CONFIG_FREERTOS_UNICORE
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void spi_flash_init()
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{
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// No-op in single core mode
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}
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static void IRAM_ATTR spi_flash_disable_interrupts_caches_and_other_cpu()
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{
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vTaskSuspendAll();
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spi_flash_disable_cache(0, &s_flash_op_cache_state[0]);
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}
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static void IRAM_ATTR spi_flash_enable_interrupts_caches_and_other_cpu()
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{
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spi_flash_restore_cache(0, s_flash_op_cache_state[0]);
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xTaskResumeAll();
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}
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#endif // CONFIG_FREERTOS_UNICORE
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SpiFlashOpResult IRAM_ATTR spi_flash_unlock()
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{
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static bool unlocked = false;
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if (!unlocked) {
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SpiFlashOpResult rc = SPIUnlock();
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if (rc != SPI_FLASH_RESULT_OK) {
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return rc;
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}
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unlocked = true;
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}
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return SPI_FLASH_RESULT_OK;
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}
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esp_err_t IRAM_ATTR spi_flash_erase_sector(uint16_t sec)
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{
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spi_flash_disable_interrupts_caches_and_other_cpu();
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SpiFlashOpResult rc;
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rc = spi_flash_unlock();
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if (rc == SPI_FLASH_RESULT_OK) {
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rc = SPIEraseSector(sec);
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}
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spi_flash_enable_interrupts_caches_and_other_cpu();
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return spi_flash_translate_rc(rc);
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}
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esp_err_t IRAM_ATTR spi_flash_write(uint32_t dest_addr, const uint32_t *src, uint32_t size)
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{
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spi_flash_disable_interrupts_caches_and_other_cpu();
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SpiFlashOpResult rc;
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rc = spi_flash_unlock();
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if (rc == SPI_FLASH_RESULT_OK) {
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rc = SPIWrite(dest_addr, src, (int32_t) size);
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}
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spi_flash_enable_interrupts_caches_and_other_cpu();
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return spi_flash_translate_rc(rc);
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}
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esp_err_t IRAM_ATTR spi_flash_read(uint32_t src_addr, uint32_t *dest, uint32_t size)
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{
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spi_flash_disable_interrupts_caches_and_other_cpu();
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SpiFlashOpResult rc;
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rc = SPIRead(src_addr, dest, (int32_t) size);
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spi_flash_enable_interrupts_caches_and_other_cpu();
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return spi_flash_translate_rc(rc);
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}
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static esp_err_t spi_flash_translate_rc(SpiFlashOpResult rc)
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{
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switch (rc) {
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case SPI_FLASH_RESULT_OK:
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return ESP_OK;
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case SPI_FLASH_RESULT_TIMEOUT:
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return ESP_ERR_FLASH_OP_TIMEOUT;
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case SPI_FLASH_RESULT_ERR:
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default:
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return ESP_ERR_FLASH_OP_FAIL;
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}
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}
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static const uint32_t cache_mask = DPORT_APP_CACHE_MASK_OPSDRAM | DPORT_APP_CACHE_MASK_DROM0 |
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DPORT_APP_CACHE_MASK_DRAM1 | DPORT_APP_CACHE_MASK_IROM0 |
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DPORT_APP_CACHE_MASK_IRAM1 | DPORT_APP_CACHE_MASK_IRAM0;
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static void IRAM_ATTR spi_flash_disable_cache(uint32_t cpuid, uint32_t* saved_state)
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{
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uint32_t ret = 0;
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if (cpuid == 0) {
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ret |= GET_PERI_REG_BITS2(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, 0);
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while (GET_PERI_REG_BITS2(DPORT_PRO_DCACHE_DBUG0_REG, DPORT_PRO_CACHE_STATE, DPORT_PRO_CACHE_STATE_S) != 1) {
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;
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}
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SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 0, DPORT_PRO_CACHE_ENABLE_S);
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} else {
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ret |= GET_PERI_REG_BITS2(DPORT_APP_CACHE_CTRL1_REG, cache_mask, 0);
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while (GET_PERI_REG_BITS2(DPORT_APP_DCACHE_DBUG0_REG, DPORT_APP_CACHE_STATE, DPORT_APP_CACHE_STATE_S) != 1) {
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;
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}
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SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 0, DPORT_APP_CACHE_ENABLE_S);
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}
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*saved_state = ret;
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}
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static void IRAM_ATTR spi_flash_restore_cache(uint32_t cpuid, uint32_t saved_state)
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{
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if (cpuid == 0) {
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SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL_REG, 1, 1, DPORT_PRO_CACHE_ENABLE_S);
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SET_PERI_REG_BITS(DPORT_PRO_CACHE_CTRL1_REG, cache_mask, saved_state, 0);
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} else {
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SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL_REG, 1, 1, DPORT_APP_CACHE_ENABLE_S);
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SET_PERI_REG_BITS(DPORT_APP_CACHE_CTRL1_REG, cache_mask, saved_state, 0);
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}
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}
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