kopia lustrzana https://github.com/espressif/esp-idf
284 wiersze
8.6 KiB
C
284 wiersze
8.6 KiB
C
// Copyright 2015-2021 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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//replacement for gcc built-in functions
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#include "sdkconfig.h"
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#include <stdbool.h>
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#include <stdint.h>
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#include "soc/soc_caps.h"
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#include "freertos/FreeRTOS.h"
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#ifdef __XTENSA__
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#include "xtensa/config/core-isa.h"
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#ifndef XCHAL_HAVE_S32C1I
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#error "XCHAL_HAVE_S32C1I not defined, include correct header!"
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#endif
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#define HAS_ATOMICS_32 (XCHAL_HAVE_S32C1I == 1)
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// no 64-bit atomics on Xtensa
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#define HAS_ATOMICS_64 0
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#else // RISCV
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// GCC toolchain will define this pre-processor if "A" extension is supported
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#ifndef __riscv_atomic
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#define __riscv_atomic 0
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#endif
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#define HAS_ATOMICS_32 (__riscv_atomic == 1)
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#define HAS_ATOMICS_64 ((__riscv_atomic == 1) && (__riscv_xlen == 64))
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#endif // (__XTENSA__, __riscv)
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#if SOC_CPU_CORES_NUM == 1
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// Single core SoC: atomics can be implemented using portENTER_CRITICAL_NESTED
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// and portEXIT_CRITICAL_NESTED, which disable and enable interrupts.
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#define _ATOMIC_ENTER_CRITICAL() ({ \
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unsigned state = portENTER_CRITICAL_NESTED(); \
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state; \
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})
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#define _ATOMIC_EXIT_CRITICAL(state) do { \
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portEXIT_CRITICAL_NESTED(state); \
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} while (0)
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#else // SOC_CPU_CORES_NUM
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_Static_assert(HAS_ATOMICS_32, "32-bit atomics should be supported if SOC_CPU_CORES_NUM > 1");
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// Only need to implement 64-bit atomics here. Use a single global portMUX_TYPE spinlock
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// to emulate the atomics.
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static portMUX_TYPE s_atomic_lock = portMUX_INITIALIZER_UNLOCKED;
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// Return value is not used but kept for compatibility with the single-core version above.
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#define _ATOMIC_ENTER_CRITICAL() ({ \
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portENTER_CRITICAL_SAFE(&s_atomic_lock); \
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0; \
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})
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#define _ATOMIC_EXIT_CRITICAL(state) do { \
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(void) (state); \
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portEXIT_CRITICAL_SAFE(&s_atomic_lock); \
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} while(0)
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#endif // SOC_CPU_CORES_NUM
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#define ATOMIC_LOAD(n, type) type __atomic_load_ ## n (const type* mem, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *mem; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define ATOMIC_STORE(n, type) void __atomic_store_ ## n (type* mem, type val, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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*mem = val; \
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_ATOMIC_EXIT_CRITICAL(state); \
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}
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#define ATOMIC_EXCHANGE(n, type) type __atomic_exchange_ ## n (type* mem, type val, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *mem; \
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*mem = val; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define CMP_EXCHANGE(n, type) bool __atomic_compare_exchange_ ## n (type* mem, type* expect, type desired, bool weak, int success, int failure) \
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{ \
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bool ret = false; \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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if (*mem == *expect) { \
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ret = true; \
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*mem = desired; \
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} else { \
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*expect = *mem; \
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} \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_ADD(n, type) type __atomic_fetch_add_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr + value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_SUB(n, type) type __atomic_fetch_sub_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr - value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_AND(n, type) type __atomic_fetch_and_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr & value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_OR(n, type) type __atomic_fetch_or_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr | value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define FETCH_XOR(n, type) type __atomic_fetch_xor_ ## n (type* ptr, type value, int memorder) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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*ptr = *ptr ^ value; \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define SYNC_FETCH_OP(op, n, type) type __sync_fetch_and_ ## op ##_ ## n (type* ptr, type value) \
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{ \
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return __atomic_fetch_ ## op ##_ ## n (ptr, value, __ATOMIC_SEQ_CST); \
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}
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#define SYNC_BOOL_CMP_EXCHANGE(n, type) bool __sync_bool_compare_and_swap_ ## n (type *ptr, type oldval, type newval) \
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{ \
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bool ret = false; \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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if (*ptr == oldval) { \
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*ptr = newval; \
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ret = true; \
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} \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#define SYNC_VAL_CMP_EXCHANGE(n, type) type __sync_val_compare_and_swap_ ## n (type *ptr, type oldval, type newval) \
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{ \
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unsigned state = _ATOMIC_ENTER_CRITICAL(); \
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type ret = *ptr; \
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if (*ptr == oldval) { \
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*ptr = newval; \
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} \
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_ATOMIC_EXIT_CRITICAL(state); \
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return ret; \
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}
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#if !HAS_ATOMICS_32
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ATOMIC_EXCHANGE(1, uint8_t)
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ATOMIC_EXCHANGE(2, uint16_t)
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ATOMIC_EXCHANGE(4, uint32_t)
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CMP_EXCHANGE(1, uint8_t)
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CMP_EXCHANGE(2, uint16_t)
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CMP_EXCHANGE(4, uint32_t)
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FETCH_ADD(1, uint8_t)
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FETCH_ADD(2, uint16_t)
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FETCH_ADD(4, uint32_t)
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FETCH_SUB(1, uint8_t)
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FETCH_SUB(2, uint16_t)
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FETCH_SUB(4, uint32_t)
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FETCH_AND(1, uint8_t)
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FETCH_AND(2, uint16_t)
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FETCH_AND(4, uint32_t)
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FETCH_OR(1, uint8_t)
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FETCH_OR(2, uint16_t)
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FETCH_OR(4, uint32_t)
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FETCH_XOR(1, uint8_t)
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FETCH_XOR(2, uint16_t)
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FETCH_XOR(4, uint32_t)
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SYNC_FETCH_OP(add, 1, uint8_t)
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SYNC_FETCH_OP(add, 2, uint16_t)
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SYNC_FETCH_OP(add, 4, uint32_t)
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SYNC_FETCH_OP(sub, 1, uint8_t)
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SYNC_FETCH_OP(sub, 2, uint16_t)
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SYNC_FETCH_OP(sub, 4, uint32_t)
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SYNC_FETCH_OP(and, 1, uint8_t)
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SYNC_FETCH_OP(and, 2, uint16_t)
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SYNC_FETCH_OP(and, 4, uint32_t)
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SYNC_FETCH_OP(or, 1, uint8_t)
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SYNC_FETCH_OP(or, 2, uint16_t)
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SYNC_FETCH_OP(or, 4, uint32_t)
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SYNC_FETCH_OP(xor, 1, uint8_t)
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SYNC_FETCH_OP(xor, 2, uint16_t)
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SYNC_FETCH_OP(xor, 4, uint32_t)
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SYNC_BOOL_CMP_EXCHANGE(1, uint8_t)
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SYNC_BOOL_CMP_EXCHANGE(2, uint16_t)
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SYNC_BOOL_CMP_EXCHANGE(4, uint32_t)
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SYNC_VAL_CMP_EXCHANGE(1, uint8_t)
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SYNC_VAL_CMP_EXCHANGE(2, uint16_t)
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SYNC_VAL_CMP_EXCHANGE(4, uint32_t)
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#endif // !HAS_ATOMICS_32
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#if !HAS_ATOMICS_64
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ATOMIC_LOAD(8, uint64_t)
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ATOMIC_STORE(8, uint64_t)
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ATOMIC_EXCHANGE(8, uint64_t)
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CMP_EXCHANGE(8, uint64_t)
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FETCH_ADD(8, uint64_t)
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FETCH_SUB(8, uint64_t)
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FETCH_AND(8, uint64_t)
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FETCH_OR(8, uint64_t)
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FETCH_XOR(8, uint64_t)
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SYNC_FETCH_OP(add, 8, uint64_t)
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SYNC_FETCH_OP(sub, 8, uint64_t)
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SYNC_FETCH_OP(and, 8, uint64_t)
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SYNC_FETCH_OP(or, 8, uint64_t)
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SYNC_FETCH_OP(xor, 8, uint64_t)
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SYNC_BOOL_CMP_EXCHANGE(8, uint64_t)
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SYNC_VAL_CMP_EXCHANGE(8, uint64_t)
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#endif // !HAS_ATOMICS_64
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