kopia lustrzana https://github.com/espressif/esp-idf
681 wiersze
24 KiB
C
681 wiersze
24 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdbool.h>
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#include <stdint.h>
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#include <stddef.h>
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#include <assert.h>
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#include "sdkconfig.h"
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#include "esp32s2/rom/ets_sys.h"
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#include "esp32s2/rom/rtc.h"
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#include "esp32s2/rom/uart.h"
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#include "esp32s2/rom/gpio.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/rtc_io_reg.h"
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#include "soc/sens_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/efuse_reg.h"
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#include "soc/syscon_reg.h"
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#include "i2c_rtc_clk.h"
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#include "soc_log.h"
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#include "sdkconfig.h"
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#include "xtensa/core-macros.h"
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static const char *TAG = "rtc_clk";
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/* PLL currently enabled, if any */
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typedef enum {
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RTC_PLL_NONE,
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RTC_PLL_320M,
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RTC_PLL_480M
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} rtc_pll_t;
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static rtc_pll_t s_cur_pll = RTC_PLL_NONE;
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/* Current CPU frequency; saved in a variable for faster freq. switching */
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static rtc_cpu_freq_t s_cur_freq = RTC_CPU_FREQ_XTAL;
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void rtc_clk_32k_enable_internal(x32k_config_t cfg)
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{
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REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DAC_XTAL_32K, cfg.dac);
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REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DRES_XTAL_32K, cfg.dres);
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REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DGM_XTAL_32K, cfg.dgm);
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REG_SET_FIELD(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_DBUF_XTAL_32K, cfg.dbuf);
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SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K);
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}
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void rtc_clk_32k_enable(bool enable)
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{
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if (enable) {
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x32k_config_t cfg = X32K_CONFIG_DEFAULT();
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rtc_clk_32k_enable_internal(cfg);
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} else {
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SET_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XTAL32K_XPD_FORCE);
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CLEAR_PERI_REG_MASK(RTC_CNTL_EXT_XTL_CONF_REG, RTC_CNTL_XPD_XTAL_32K);
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}
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}
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void rtc_clk_32k_bootstrap(uint32_t cycle)
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{
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}
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bool rtc_clk_32k_enabled(void)
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{
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uint32_t xtal_conf = READ_PERI_REG(RTC_CNTL_EXT_XTL_CONF_REG);
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/* If xtal xpd is controlled by software */
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bool xtal_xpd_sw = (xtal_conf & RTC_CNTL_XTAL32K_XPD_FORCE) >> RTC_CNTL_XTAL32K_XPD_FORCE_S;
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/* If xtal xpd software control is on */
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bool xtal_xpd_st = (xtal_conf & RTC_CNTL_XPD_XTAL_32K) >> RTC_CNTL_XPD_XTAL_32K_S;
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if (xtal_xpd_sw & !xtal_xpd_st) {
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return false;
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} else {
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return true;
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}
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}
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void rtc_clk_8m_enable(bool clk_8m_en, bool d256_en)
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{
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if (clk_8m_en) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
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/* no need to wait once enabled by software */
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CK8M_ENABLE_WAIT_DEFAULT);
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ets_delay_us(DELAY_8M_ENABLE);
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} else {
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_DEFAULT);
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}
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/* d256 should be independent configured with 8M
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* Maybe we can split this function into 8m and dmd256
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*/
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if (d256_en) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
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} else {
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV);
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}
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}
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bool rtc_clk_8m_enabled(void)
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{
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return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M) == 0;
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}
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bool rtc_clk_8md256_enabled(void)
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{
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return GET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ENB_CK8M_DIV) == 0;
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}
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void rtc_clk_apll_enable(bool enable, uint32_t sdm0, uint32_t sdm1, uint32_t sdm2, uint32_t o_div)
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{
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REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD, enable ? 0 : 1);
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REG_SET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU, enable ? 1 : 0);
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/* BIAS I2C not exist any more, but not sure how to get the same effect yet...
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* if (!enable &&
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* REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL) != DPORT_SOC_CLK_SEL_PLL) {
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* REG_SET_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
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* } else {
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* REG_CLR_BIT(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
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* }
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*/
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if (enable) {
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/* no need to differentiate ECO chip any more
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uint8_t sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV1;
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uint32_t is_rev0 = (GET_PERI_REG_BITS2(EFUSE_BLK0_RDATA3_REG, 1, 15) == 0);
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if (is_rev0) {
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sdm0 = 0;
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sdm1 = 0;
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sdm_stop_val_2 = APLL_SDM_STOP_VAL_2_REV0;
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}
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*/
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I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM2, sdm2);
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I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM0, sdm0);
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I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_DSDM1, sdm1);
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I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_1);
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I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_SDM_STOP, APLL_SDM_STOP_VAL_2_REV1);
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I2C_WRITEREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_OUTPUT_DIV, o_div);
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/* calibration */
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I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_1);
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I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_2);
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I2C_WRITEREG_RTC(I2C_APLL, I2C_APLL_IR_CAL_DELAY, APLL_CAL_DELAY_3);
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/* wait for calibration end */
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while (!(I2C_READREG_MASK_RTC(I2C_APLL, I2C_APLL_OR_CAL_END))) {
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/* use ets_delay_us so the RTC bus doesn't get flooded */
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ets_delay_us(1);
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}
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}
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}
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void rtc_clk_set_xtal_wait(void)
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{
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/*
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the `xtal_wait` time need 1ms, so we need calibrate slow clk period,
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and `RTC_CNTL_XTL_BUF_WAIT` depend on it.
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*/
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rtc_slow_freq_t slow_clk_freq = rtc_clk_slow_freq_get();
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rtc_slow_freq_t rtc_slow_freq_x32k = RTC_SLOW_FREQ_32K_XTAL;
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rtc_slow_freq_t rtc_slow_freq_8MD256 = RTC_SLOW_FREQ_8MD256;
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rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
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if (slow_clk_freq == (rtc_slow_freq_x32k)) {
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cal_clk = RTC_CAL_32K_XTAL;
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} else if (slow_clk_freq == rtc_slow_freq_8MD256) {
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cal_clk = RTC_CAL_8MD256;
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}
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uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 2000);
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uint32_t xtal_wait_1ms = 100;
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if (slow_clk_period) {
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xtal_wait_1ms = (1000 << RTC_CLK_CAL_FRACT) / slow_clk_period;
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}
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, xtal_wait_1ms);
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}
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void rtc_clk_slow_freq_set(rtc_slow_freq_t slow_freq)
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{
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL, slow_freq);
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/* Why we need to connect this clock to digital?
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* Or maybe this clock should be connected to digital when xtal 32k clock is enabled instead?
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*/
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_DIG_XTAL32K_EN,
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(slow_freq == RTC_SLOW_FREQ_32K_XTAL) ? 1 : 0);
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/* The clk_8m_d256 will be closed when rtc_state in SLEEP,
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so if the slow_clk is 8md256, clk_8m must be force power on
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*/
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU, (slow_freq == RTC_SLOW_FREQ_8MD256) ? 1 : 0);
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rtc_clk_set_xtal_wait();
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ets_delay_us(DELAY_SLOW_CLK_SWITCH);
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}
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rtc_slow_freq_t rtc_clk_slow_freq_get(void)
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{
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return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_ANA_CLK_RTC_SEL);
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}
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uint32_t rtc_clk_slow_freq_get_hz(void)
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{
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switch (rtc_clk_slow_freq_get()) {
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case RTC_SLOW_FREQ_RTC: return RTC_SLOW_CLK_FREQ_150K;
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case RTC_SLOW_FREQ_32K_XTAL: return RTC_SLOW_CLK_FREQ_32K;
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case RTC_SLOW_FREQ_8MD256: return RTC_SLOW_CLK_FREQ_8MD256;
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}
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return 0;
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}
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void rtc_clk_fast_freq_set(rtc_fast_freq_t fast_freq)
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{
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL, fast_freq);
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ets_delay_us(DELAY_FAST_CLK_SWITCH);
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}
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rtc_fast_freq_t rtc_clk_fast_freq_get(void)
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{
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return REG_GET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_FAST_CLK_RTC_SEL);
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}
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/* In 7.2.2, cpu can run at 80M/160M/240M if PLL is 480M
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* pll can run 80M/160M is PLL is 320M
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*/
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#define DR_REG_I2C_MST_BASE 0x3f40E000
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#define I2C_MST_ANA_STATE_REG (DR_REG_I2C_MST_BASE + 0x040)
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#define I2C_MST_BBPLL_CAL_END (BIT(24))
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#define I2C_MST_BBPLL_CAL_END_M (BIT(24))
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#define I2C_MST_BBPLL_CAL_END_V 0x1
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#define I2C_MST_BBPLL_CAL_END_S 24
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void rtc_clk_bbpll_set(rtc_xtal_freq_t xtal_freq, rtc_pll_t pll_freq)
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{
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uint8_t div_ref;
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uint8_t div7_0;
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uint8_t dr1;
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uint8_t dr3;
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uint8_t dchgp;
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uint8_t dcur;
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assert(xtal_freq == RTC_XTAL_FREQ_40M);
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if (pll_freq == RTC_PLL_480M) {
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/* Raise the voltage, if needed */
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/* move to 240M logic */
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//REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
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/* Set this register to let digital know pll is 480M */
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SET_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL);
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/* Configure 480M PLL */
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div_ref = 0;
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div7_0 = 8;
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dr1 = 0;
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dr3 = 0;
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dchgp = 5;
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dcur = 4;
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x6B);
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} else {
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/* Raise the voltage */
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//REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
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//ets_delay_us(DELAY_PLL_DBIAS_RAISE);
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CLEAR_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL);
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/* Configure 480M PLL */
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div_ref = 0;
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div7_0 = 4;
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dr1 = 0;
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dr3 = 0;
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dchgp = 5;
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dcur = 5;
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_MODE_HF, 0x69);
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}
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uint8_t i2c_bbpll_lref = (dchgp << I2C_BBPLL_OC_DCHGP_LSB) | (div_ref);
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uint8_t i2c_bbpll_div_7_0 = div7_0;
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uint8_t i2c_bbpll_dcur = (2 << I2C_BBPLL_OC_DLREF_SEL_LSB ) | (1 << I2C_BBPLL_OC_DHREF_SEL_LSB) | dcur;
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_REF_DIV, i2c_bbpll_lref);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DIV_7_0, i2c_bbpll_div_7_0);
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I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR1, dr1);
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I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OC_DR3, dr3);
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I2C_WRITEREG_RTC(I2C_BBPLL, I2C_BBPLL_OC_DCUR, i2c_bbpll_dcur);
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// Enable calibration by software
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I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_ENX_CAP, 1);
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for (int ext_cap = 0; ext_cap < 16; ext_cap++) {
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uint8_t cal_result;
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I2C_WRITEREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_IR_CAL_EXT_CAP, ext_cap);
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cal_result = I2C_READREG_MASK_RTC(I2C_BBPLL, I2C_BBPLL_OR_CAL_CAP);
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if (cal_result == 0) {
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break;
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}
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if (ext_cap == 15) {
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SOC_LOGE(TAG, "BBPLL SOFTWARE CAL FAIL");
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}
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}
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/* this delay is replaced by polling Pll calibration end flag
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* uint32_t delay_pll_en = (rtc_clk_slow_freq_get() == RTC_SLOW_FREQ_RTC) ?
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* DELAY_PLL_ENABLE_WITH_150K : DELAY_PLL_ENABLE_WITH_32K;
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* ets_delay_us(delay_pll_en);
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*/
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/* this calibration didn't work on 480M
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need to test exact delay according to 320M
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while (!GET_PERI_REG_MASK(I2C_MST_ANA_STATE_REG, I2C_MST_BBPLL_CAL_END)) {
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ets_delay_us(1);
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}
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*/
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}
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/**
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* Switch to XTAL frequency. Does not disable the PLL.
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*/
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static void rtc_clk_cpu_freq_to_xtal(void)
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{
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rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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ets_update_cpu_frequency(xtal_freq);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
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REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0);
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REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, 0);
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/* Why we need to do this ? */
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//DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0); // clear DPORT_CPUPERIOD_SEL
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rtc_clk_apb_freq_update(xtal_freq * MHZ);
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s_cur_freq = RTC_CPU_FREQ_XTAL;
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s_cur_pll = RTC_PLL_NONE;
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}
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/**
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* Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
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* PLL must already be enabled.
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* If switching between frequencies derived from different PLLs (320M and 480M),
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* fall back to rtc_clk_cpu_freq_set.
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* @param cpu_freq new CPU frequency
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*/
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static void rtc_clk_cpu_freq_to_pll(rtc_cpu_freq_t cpu_freq)
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{
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int freq = 0;
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if ((s_cur_pll == RTC_PLL_NONE) || ((s_cur_pll == RTC_PLL_320M) && (cpu_freq == RTC_CPU_FREQ_240M))) {
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/*
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* if switch from non-pll or switch from PLL 320M to 480M
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* need to switch PLLs, fall back to full implementation
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*/
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rtc_clk_cpu_freq_set(cpu_freq);
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return;
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}
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if ((cpu_freq == RTC_CPU_FREQ_80M) || (cpu_freq == RTC_CPU_320M_80M)) {
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
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DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 0);
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freq = 80;
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} else if ((cpu_freq == RTC_CPU_FREQ_160M) || (cpu_freq == RTC_CPU_320M_160M)) {
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
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DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 1);
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freq = 160;
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} else if (cpu_freq == RTC_CPU_FREQ_240M) {
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
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DPORT_REG_WRITE(DPORT_CPU_PER_CONF_REG, 2);
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freq = 240;
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}
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// REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, DPORT_SOC_CLK_SEL_PLL);
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rtc_clk_apb_freq_update(80 * MHZ);
|
|
ets_update_cpu_frequency(freq);
|
|
s_cur_freq = cpu_freq;
|
|
}
|
|
|
|
void rtc_clk_cpu_freq_set_fast(rtc_cpu_freq_t cpu_freq)
|
|
{
|
|
if (cpu_freq == s_cur_freq) {
|
|
return;
|
|
} else if (cpu_freq == RTC_CPU_FREQ_2M || s_cur_freq == RTC_CPU_FREQ_2M) {
|
|
/* fall back to full implementation if switch to/from 2M is needed */
|
|
rtc_clk_cpu_freq_set(cpu_freq);
|
|
} else if (cpu_freq == RTC_CPU_FREQ_XTAL) {
|
|
rtc_clk_cpu_freq_to_xtal();
|
|
} else if (cpu_freq > RTC_CPU_FREQ_XTAL) {
|
|
rtc_clk_cpu_freq_to_pll(cpu_freq);
|
|
/* Not neccessary any more */
|
|
//rtc_clk_wait_for_slow_cycle();
|
|
}
|
|
}
|
|
|
|
void rtc_clk_cpu_freq_set(rtc_cpu_freq_t cpu_freq)
|
|
{
|
|
rtc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
|
|
/* Switch CPU to XTAL frequency first */
|
|
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_XTAL);
|
|
REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, 0);
|
|
REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, 0);
|
|
ets_update_cpu_frequency(xtal_freq);
|
|
/* Frequency switch is synchronized to SLOW_CLK cycle. Wait until the switch
|
|
* is complete before disabling the PLL.
|
|
*/
|
|
/* register SOC_CLK_SEL is moved to APB domain, so this delay is not neccessary any more */
|
|
//rtc_clk_wait_for_slow_cycle();
|
|
|
|
DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
|
|
|
|
/* BBPLL force power down won't affect force power up setting */
|
|
SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
|
|
RTC_CNTL_BB_I2C_FORCE_PD | RTC_CNTL_BBPLL_FORCE_PD |
|
|
RTC_CNTL_BBPLL_I2C_FORCE_PD);
|
|
s_cur_pll = RTC_PLL_NONE;
|
|
rtc_clk_apb_freq_update(xtal_freq * MHZ);
|
|
|
|
/* is APLL under force power down? */
|
|
/* may need equivalent function
|
|
uint32_t apll_fpd = REG_GET_FIELD(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
|
|
|
|
* if (apll_fpd) {
|
|
* SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BIAS_I2C_FORCE_PD);
|
|
* }
|
|
*/
|
|
|
|
/* now switch to the desired frequency */
|
|
if (cpu_freq == RTC_CPU_FREQ_XTAL) {
|
|
/* already at XTAL, nothing to do */
|
|
} else if (cpu_freq == RTC_CPU_FREQ_2M) {
|
|
/* set up divider to produce 2MHz from XTAL */
|
|
REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT, (xtal_freq / 2) - 1);
|
|
ets_update_cpu_frequency(2);
|
|
rtc_clk_apb_freq_update(2 * MHZ);
|
|
/* lower the voltage */
|
|
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_2M);
|
|
} else {
|
|
/* use PLL as clock source */
|
|
CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG,
|
|
RTC_CNTL_BB_I2C_FORCE_PD |
|
|
RTC_CNTL_BBPLL_FORCE_PD | RTC_CNTL_BBPLL_I2C_FORCE_PD);
|
|
if (cpu_freq > RTC_CPU_FREQ_2M) {
|
|
rtc_clk_bbpll_set(xtal_freq, RTC_PLL_320M);
|
|
s_cur_pll = RTC_PLL_320M;
|
|
} else {
|
|
rtc_clk_bbpll_set(xtal_freq, RTC_PLL_480M);
|
|
s_cur_pll = RTC_PLL_480M;
|
|
}
|
|
|
|
if ((cpu_freq == RTC_CPU_FREQ_80M) || (cpu_freq == RTC_CPU_320M_80M)) {
|
|
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
|
|
DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 0);
|
|
ets_update_cpu_frequency(80);
|
|
} else if ((cpu_freq == RTC_CPU_FREQ_160M) || (cpu_freq == RTC_CPU_320M_160M)) {
|
|
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_80M_160M);
|
|
DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 1);
|
|
ets_update_cpu_frequency(160);
|
|
} else if (cpu_freq == RTC_CPU_FREQ_240M) {
|
|
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DIG_DBIAS_WAK, DIG_DBIAS_240M);
|
|
DPORT_REG_SET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL, 2);
|
|
ets_update_cpu_frequency(240);
|
|
}
|
|
REG_SET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL, 1);
|
|
//rtc_clk_wait_for_slow_cycle();
|
|
rtc_clk_apb_freq_update(80 * MHZ);
|
|
}
|
|
s_cur_freq = cpu_freq;
|
|
}
|
|
|
|
rtc_cpu_freq_t rtc_clk_cpu_freq_get(void)
|
|
{
|
|
uint32_t soc_clk_sel = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL);
|
|
switch (soc_clk_sel) {
|
|
case 0: {
|
|
uint32_t pre_div = REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_PRE_DIV_CNT);
|
|
if (pre_div == 0) {
|
|
return RTC_CPU_FREQ_XTAL;
|
|
} else if (pre_div == 1) {
|
|
return RTC_CPU_FREQ_XTAL_DIV2;
|
|
} else if (pre_div == rtc_clk_xtal_freq_get() / 2 - 1) {
|
|
return RTC_CPU_FREQ_2M;
|
|
} else {
|
|
assert(false && "unsupported frequency");
|
|
}
|
|
break;
|
|
}
|
|
case 1: {
|
|
uint32_t cpuperiod_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_CPUPERIOD_SEL);
|
|
uint32_t pllfreq_sel = DPORT_REG_GET_FIELD(DPORT_CPU_PER_CONF_REG, DPORT_PLL_FREQ_SEL);
|
|
if (cpuperiod_sel == 0) {
|
|
if (pllfreq_sel == 1) {
|
|
return RTC_CPU_FREQ_80M;
|
|
} else {
|
|
return RTC_CPU_320M_80M;
|
|
}
|
|
} else if (cpuperiod_sel == 1) {
|
|
if (pllfreq_sel == 1) {
|
|
return RTC_CPU_FREQ_160M;
|
|
} else {
|
|
return RTC_CPU_320M_160M;
|
|
}
|
|
} else if (cpuperiod_sel == 2) {
|
|
return RTC_CPU_FREQ_240M;
|
|
} else {
|
|
assert(false && "unsupported frequency");
|
|
}
|
|
break;
|
|
}
|
|
case 2:
|
|
case 3:
|
|
default:
|
|
assert(false && "unsupported frequency");
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
uint32_t rtc_clk_cpu_freq_value(rtc_cpu_freq_t cpu_freq)
|
|
{
|
|
switch (cpu_freq) {
|
|
case RTC_CPU_FREQ_XTAL:
|
|
return ((uint32_t) rtc_clk_xtal_freq_get()) * MHZ;
|
|
case RTC_CPU_FREQ_XTAL_DIV2:
|
|
return ((uint32_t) rtc_clk_xtal_freq_get()) / 2 * MHZ;
|
|
case RTC_CPU_FREQ_2M:
|
|
return 2 * MHZ;
|
|
case RTC_CPU_FREQ_80M:
|
|
return 80 * MHZ;
|
|
case RTC_CPU_FREQ_160M:
|
|
return 160 * MHZ;
|
|
case RTC_CPU_FREQ_240M:
|
|
return 240 * MHZ;
|
|
case RTC_CPU_320M_80M:
|
|
return 80 * MHZ;
|
|
case RTC_CPU_320M_160M:
|
|
return 160 * MHZ;
|
|
default:
|
|
assert(false && "invalid rtc_cpu_freq_t value");
|
|
return 0;
|
|
}
|
|
}
|
|
|
|
bool rtc_clk_cpu_freq_from_mhz(int mhz, rtc_cpu_freq_t *out_val)
|
|
{
|
|
if (mhz == 240) {
|
|
*out_val = RTC_CPU_FREQ_240M;
|
|
} else if (mhz == 160) {
|
|
*out_val = RTC_CPU_FREQ_160M;
|
|
} else if (mhz == 80) {
|
|
*out_val = RTC_CPU_FREQ_80M;
|
|
} else if (mhz == (int) rtc_clk_xtal_freq_get()) {
|
|
*out_val = RTC_CPU_FREQ_XTAL;
|
|
} else if (mhz == (int) rtc_clk_xtal_freq_get() / 2) {
|
|
*out_val = RTC_CPU_FREQ_XTAL_DIV2;
|
|
} else if (mhz == 2) {
|
|
*out_val = RTC_CPU_FREQ_2M;
|
|
} else {
|
|
return false;
|
|
}
|
|
return true;
|
|
}
|
|
|
|
/* Values of RTC_XTAL_FREQ_REG and RTC_APB_FREQ_REG are stored as two copies in
|
|
* lower and upper 16-bit halves. These are the routines to work with such a
|
|
* representation.
|
|
*/
|
|
static bool clk_val_is_valid(uint32_t val)
|
|
{
|
|
return (val & 0xffff) == ((val >> 16) & 0xffff) &&
|
|
val != 0 &&
|
|
val != UINT32_MAX;
|
|
}
|
|
|
|
static uint32_t reg_val_to_clk_val(uint32_t val)
|
|
{
|
|
return val & UINT16_MAX;
|
|
}
|
|
|
|
static uint32_t clk_val_to_reg_val(uint32_t val)
|
|
{
|
|
return (val & UINT16_MAX) | ((val & UINT16_MAX) << 16);
|
|
}
|
|
|
|
rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
|
|
{
|
|
uint32_t xtal_freq_reg = READ_PERI_REG(RTC_XTAL_FREQ_REG);
|
|
if (!clk_val_is_valid(xtal_freq_reg)) {
|
|
SOC_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value: 0x%08x", xtal_freq_reg);
|
|
return RTC_XTAL_FREQ_40M;
|
|
}
|
|
return reg_val_to_clk_val(xtal_freq_reg);
|
|
}
|
|
|
|
void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
|
|
{
|
|
WRITE_PERI_REG(RTC_XTAL_FREQ_REG, clk_val_to_reg_val(xtal_freq));
|
|
}
|
|
|
|
void rtc_clk_apb_freq_update(uint32_t apb_freq)
|
|
{
|
|
WRITE_PERI_REG(RTC_APB_FREQ_REG, clk_val_to_reg_val(apb_freq >> 12));
|
|
}
|
|
|
|
uint32_t rtc_clk_apb_freq_get(void)
|
|
{
|
|
uint32_t freq_hz = reg_val_to_clk_val(READ_PERI_REG(RTC_APB_FREQ_REG)) << 12;
|
|
// round to the nearest MHz
|
|
freq_hz += MHZ / 2;
|
|
uint32_t remainder = freq_hz % MHZ;
|
|
return freq_hz - remainder;
|
|
}
|
|
|
|
void rtc_clk_divider_set(uint32_t div)
|
|
{
|
|
CLEAR_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
|
|
REG_SET_FIELD(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV, div);
|
|
SET_PERI_REG_MASK(RTC_CNTL_SLOW_CLK_CONF_REG, RTC_CNTL_ANA_CLK_DIV_VLD);
|
|
}
|
|
|
|
void rtc_clk_8m_divider_set(uint32_t div)
|
|
{
|
|
CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
|
|
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL, div);
|
|
SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DIV_SEL_VLD);
|
|
}
|
|
|
|
void rtc_clk_init(rtc_clk_config_t cfg)
|
|
{
|
|
rtc_cpu_freq_t cpu_source_before = rtc_clk_cpu_freq_get();
|
|
/* If we get a TG WDT system reset while running at 240MHz,
|
|
* DPORT_CPUPERIOD_SEL register will be reset to 0 resulting in 120MHz
|
|
* APB and CPU frequencies after reset. This will cause issues with XTAL
|
|
* frequency estimation, so we switch to XTAL frequency first.
|
|
*
|
|
* Ideally we would only do this if SYSCON_SOC_CLK_SEL == PLL and
|
|
* PLL is configured for 480M, but it takes less time to switch to 40M and
|
|
* run the following code than querying the PLL does.
|
|
*/
|
|
if (REG_GET_FIELD(DPORT_SYSCLK_CONF_REG, DPORT_SOC_CLK_SEL) == 1) {
|
|
rtc_clk_cpu_freq_set(RTC_CPU_FREQ_XTAL);
|
|
}
|
|
|
|
/* Set tuning parameters for 8M and 150k clocks.
|
|
* Note: this doesn't attempt to set the clocks to precise frequencies.
|
|
* Instead, we calibrate these clocks against XTAL frequency later, when necessary.
|
|
* - SCK_DCAP value controls tuning of 150k clock.
|
|
* The higher the value of DCAP is, the lower is the frequency.
|
|
* - CK8M_DFREQ value controls tuning of 8M clock.
|
|
* CLK_8M_DFREQ constant gives the best temperature characteristics.
|
|
*/
|
|
REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
|
|
REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
|
|
|
|
/* Configure 150k clock division */
|
|
rtc_clk_divider_set(cfg.clk_rtc_clk_div);
|
|
/* Configure 8M clock division */
|
|
rtc_clk_8m_divider_set(cfg.clk_8m_clk_div);
|
|
|
|
/* Enable the internal bus used to configure PLLs */
|
|
SET_PERI_REG_BITS(ANA_CONFIG_REG, ANA_CONFIG_M, ANA_CONFIG_M, ANA_CONFIG_S);
|
|
CLEAR_PERI_REG_MASK(ANA_CONFIG_REG, I2C_APLL_M | I2C_BBPLL_M);
|
|
|
|
rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
|
|
uart_tx_wait_idle(0);
|
|
rtc_clk_xtal_freq_update(xtal_freq);
|
|
rtc_clk_apb_freq_update(xtal_freq * MHZ);
|
|
/* Set CPU frequency */
|
|
rtc_clk_cpu_freq_set(cfg.cpu_freq);
|
|
|
|
/* Re-calculate the ccount to make time calculation correct. */
|
|
uint32_t freq_before = rtc_clk_cpu_freq_value(cpu_source_before) / MHZ;
|
|
uint32_t freq_after = rtc_clk_cpu_freq_value(cfg.cpu_freq) / MHZ;
|
|
XTHAL_SET_CCOUNT( XTHAL_GET_CCOUNT() * freq_after / freq_before );
|
|
|
|
/* Slow & fast clocks setup */
|
|
if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
|
|
rtc_clk_32k_enable(true);
|
|
}
|
|
if (cfg.fast_freq == RTC_FAST_FREQ_8M) {
|
|
bool need_8md256 = cfg.slow_freq == RTC_SLOW_FREQ_8MD256;
|
|
rtc_clk_8m_enable(true, need_8md256);
|
|
}
|
|
rtc_clk_fast_freq_set(cfg.fast_freq);
|
|
rtc_clk_slow_freq_set(cfg.slow_freq);
|
|
}
|
|
|
|
/* Name used in libphy.a:phy_chip_v7.o
|
|
* TODO: update the library to use rtc_clk_xtal_freq_get
|
|
*/
|
|
rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));
|