Marius Vikhammer c36dd7834f core: fix cases where riscv SP were not 16 byte aligned ... RISC-V stack pointer should always be 16 byte aligned, but for some cases where we were doing manual SP manipulation this was not always the case.		2021-02-19 11:26:21 +08:00
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include/freertos	…
port	core: fix cases where riscv SP were not 16 byte aligned	2021-02-19 11:26:21 +08:00
test	system: enable shared stack watchpoint	2021-02-18 15:38:30 +08:00
CMakeLists.txt	…
FreeRTOS-openocd.c	…
History.txt	…
Kconfig	…
component.mk	…
croutine.c	…
event_groups.c	freertos: fix errors reported by PVS-Studio	2021-02-11 03:15:04 +00:00
freertos_v8_compat.c	…
license.txt	…
linker.lf	…
list.c	…
queue.c	…
sdkconfig.rename	…
stream_buffer.c	…
tasks.c	freertos: fix errors reported by PVS-Studio	2021-02-11 03:15:04 +00:00
timers.c	…