kopia lustrzana https://github.com/espressif/esp-idf
548 wiersze
16 KiB
C
548 wiersze
16 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*******************************************************************************
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* NOTICE
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* The hal is not public api, don't use in application code.
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* See readme.md in hal/include/hal/readme.md
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******************************************************************************/
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// The LL layer for ESP32 SDIO slave register operations
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// It's strange but `tx_*` regs for host->slave transfers while `rx_*` regs for slave->host transfers
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// To reduce ambiguity, we call (host->slave, tx) transfers receiving and (slave->host, rx) transfers receiving
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#pragma once
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#include "hal/sdio_slave_types.h"
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#include "soc/slc_struct.h"
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#include "soc/slc_reg.h"
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#include "soc/host_struct.h"
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#include "soc/host_reg.h"
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#include "soc/hinf_struct.h"
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#include "soc/lldesc.h"
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#include "soc/dport_reg.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/// Get address of the only SLC registers for ESP32
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#define sdio_slave_ll_get_slc(ID) (&SLC)
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/// Get address of the only HOST registers for ESP32
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#define sdio_slave_ll_get_host(ID) (&HOST)
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/// Get address of the only HINF registers for ESP32
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#define sdio_slave_ll_get_hinf(ID) (&HINF)
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/*
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* SLC2 DMA Desc struct, aka sdio_slave_ll_desc_t
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*
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* --------------------------------------------------------------
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* | own | EoF | sub_sof | 5'b0 | length [11:0] | size [11:0] |
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* --------------------------------------------------------------
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* | buf_ptr [31:0] |
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* --------------------------------------------------------------
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* | next_desc_ptr [31:0] |
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* --------------------------------------------------------------
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*/
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/* this bitfield is start from the LSB!!! */
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typedef struct sdio_slave_ll_desc_s {
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volatile uint32_t size : 12,
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length: 12,
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offset: 5, /* starting from bit24, h/w reserved 5bit, s/w use it as offset in buffer */
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sosf : 1, /* start of sub-frame */
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eof : 1, /* end of frame */
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owner : 1; /* hw or sw */
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volatile const uint8_t *buf; /* point to buffer data */
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union {
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volatile uint32_t empty;
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STAILQ_ENTRY(sdio_slave_ll_desc_s) qe; /* pointing to the next desc */
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};
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} sdio_slave_ll_desc_t;
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/// Mask of general purpose interrupts sending from the host.
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typedef enum {
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SDIO_SLAVE_LL_SLVINT_0 = BIT(0), ///< General purpose interrupt bit 0.
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SDIO_SLAVE_LL_SLVINT_1 = BIT(1),
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SDIO_SLAVE_LL_SLVINT_2 = BIT(2),
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SDIO_SLAVE_LL_SLVINT_3 = BIT(3),
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SDIO_SLAVE_LL_SLVINT_4 = BIT(4),
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SDIO_SLAVE_LL_SLVINT_5 = BIT(5),
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SDIO_SLAVE_LL_SLVINT_6 = BIT(6),
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SDIO_SLAVE_LL_SLVINT_7 = BIT(7),
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} sdio_slave_ll_slvint_t;
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/**
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* @brief Enable the bus clock for the SDIO slave module
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*
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* @param enable true to enable, false to disable
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*/
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static inline void _sdio_slave_ll_enable_bus_clock(bool enable)
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{
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uint32_t reg_val = DPORT_READ_PERI_REG(DPORT_WIFI_CLK_EN_REG);
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reg_val &= ~DPORT_WIFI_CLK_SDIOSLAVE_EN;
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reg_val |= enable << 4;
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DPORT_WRITE_PERI_REG(DPORT_WIFI_CLK_EN_REG, reg_val);
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define sdio_slave_ll_enable_bus_clock(...) (void)__DECLARE_RCC_ATOMIC_ENV; _sdio_slave_ll_enable_bus_clock(__VA_ARGS__)
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/**
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* @brief Reset the SDIO slave module
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*/
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static inline void _sdio_slave_ll_reset_register(void)
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{
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DPORT_WRITE_PERI_REG(DPORT_CORE_RST_EN_REG, DPORT_SDIO_RST);
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DPORT_WRITE_PERI_REG(DPORT_CORE_RST_EN_REG, 0);
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}
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/// use a macro to wrap the function, force the caller to use it in a critical section
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/// the critical section needs to declare the __DECLARE_RCC_ATOMIC_ENV variable in advance
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#define sdio_slave_ll_reset_register(...) (void)__DECLARE_RCC_ATOMIC_ENV; _sdio_slave_ll_reset_register(__VA_ARGS__)
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/**
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* Initialize the hardware.
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*
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* @param slc Address of the SLC registers
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*/
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static inline void sdio_slave_ll_init(slc_dev_t *slc)
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{
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slc->slc0_int_ena.val = 0;
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slc->conf0.slc0_rx_auto_wrback = 1;
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slc->conf0.slc0_token_auto_clr = 0;
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slc->conf0.slc0_rx_loop_test = 0;
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slc->conf0.slc0_tx_loop_test = 0;
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slc->conf1.slc0_rx_stitch_en = 0;
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slc->conf1.slc0_tx_stitch_en = 0;
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slc->conf1.slc0_len_auto_clr = 0;
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slc->rx_dscr_conf.slc0_token_no_replace = 1;
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}
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/**
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* Set the timing for the communication
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*
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* @param host Address of the host registers
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* @param timing Timing configuration to set
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*/
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static inline void sdio_slave_ll_set_timing(host_dev_t *host, sdio_slave_timing_t timing)
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{
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switch (timing) {
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case SDIO_SLAVE_TIMING_PSEND_PSAMPLE:
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host->conf.frc_sdio20 = 0x1f;
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host->conf.frc_sdio11 = 0;
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host->conf.frc_pos_samp = 0x1f;
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host->conf.frc_neg_samp = 0;
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break;
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case SDIO_SLAVE_TIMING_PSEND_NSAMPLE:
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host->conf.frc_sdio20 = 0x1f;
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host->conf.frc_sdio11 = 0;
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host->conf.frc_pos_samp = 0;
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host->conf.frc_neg_samp = 0x1f;
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break;
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case SDIO_SLAVE_TIMING_NSEND_PSAMPLE:
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host->conf.frc_sdio20 = 0;
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host->conf.frc_sdio11 = 0x1f;
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host->conf.frc_pos_samp = 0x1f;
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host->conf.frc_neg_samp = 0;
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break;
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case SDIO_SLAVE_TIMING_NSEND_NSAMPLE:
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host->conf.frc_sdio20 = 0;
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host->conf.frc_sdio11 = 0x1f;
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host->conf.frc_pos_samp = 0;
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host->conf.frc_neg_samp = 0x1f;
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break;
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}
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}
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/**
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* Set the CCCR, SDIO and Physical Layer version
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*/
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static inline void sdio_slave_ll_init_version(hinf_dev_t *hinf)
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{
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hinf->cfg_data1.sdio_ver = 0x232;
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}
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/**
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* Set the HS supported bit to be read by the host.
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*
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* @param hinf Address of the hinf registers
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* @param hs true if supported, otherwise false.
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*/
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static inline void sdio_slave_ll_enable_hs(hinf_dev_t *hinf, bool hs)
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{
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if (hs) {
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hinf->cfg_data1.highspeed_enable = 1;
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} else {
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hinf->cfg_data1.highspeed_enable = 0;
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}
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}
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/**
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* Set the IO Ready bit to be read by the host.
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*
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* @param hinf Address of the hinf registers
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* @param ready true if ready, otherwise false.
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*/
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static inline void sdio_slave_ll_set_ioready(hinf_dev_t *hinf, bool ready)
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{
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hinf->cfg_data1.sdio_ioready1 = (ready ? 1 : 0); //set IO ready to 1 to stop host from using
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}
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/*---------------------------------------------------------------------------
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* Send
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*--------------------------------------------------------------------------*/
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/**
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* Reset the sending DMA.
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*
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* @param slc Address of the SLC registers
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*/
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static inline void sdio_slave_ll_send_reset(slc_dev_t *slc)
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{
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//reset to flush previous packets
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slc->conf0.slc0_rx_rst = 1;
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slc->conf0.slc0_rx_rst = 0;
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}
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/**
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* Start the sending DMA with the given descriptor.
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*
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* @param slc Address of the SLC registers
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* @param desc Descriptor to send
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*/
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static inline void sdio_slave_ll_send_start(slc_dev_t *slc, const sdio_slave_ll_desc_t *desc)
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{
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slc->slc0_rx_link.addr = (uint32_t)desc;
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slc->slc0_rx_link.start = 1;
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}
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/**
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* Write the PKT_LEN register to be written by the host to a certain value.
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*
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* @param slc Address of the SLC registers
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* @param len Length to write
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*/
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static inline void sdio_slave_ll_send_write_len(slc_dev_t *slc, uint32_t len)
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{
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slc->slc0_len_conf.val = FIELD_TO_VALUE2(SLC_SLC0_LEN_WDATA, len) | FIELD_TO_VALUE2(SLC_SLC0_LEN_WR, 1);
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}
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/**
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* Read the value of PKT_LEN register. The register may keep the same until read
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* by the host.
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*
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* @param host Address of the host registers
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* @return The value of PKT_LEN register.
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*/
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static inline uint32_t sdio_slave_ll_send_read_len(host_dev_t *host)
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{
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return host->pkt_len.reg_slc0_len;
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}
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/**
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* Enable the rx_done interrupt. (sending)
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*
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* @param slc Address of the SLC registers
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* @param ena true if enable, otherwise false.
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*/
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static inline void sdio_slave_ll_send_part_done_intr_ena(slc_dev_t *slc, bool ena)
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{
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slc->slc0_int_ena.rx_done = (ena ? 1 : 0);
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}
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/**
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* Clear the rx_done interrupt. (sending)
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*
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* @param slc Address of the SLC registers
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*/
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static inline void sdio_slave_ll_send_part_done_clear(slc_dev_t *slc)
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{
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slc->slc0_int_clr.rx_done = 1;
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}
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/**
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* Check whether the hardware is ready for the SW to use rx_done to invoke
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* the ISR.
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*
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* @param slc Address of the SLC registers
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* @return true if ready, otherwise false.
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*/
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static inline bool sdio_slave_ll_send_invoker_ready(slc_dev_t *slc)
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{
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return slc->slc0_int_raw.rx_done;
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}
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/**
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* Stop the sending DMA.
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*
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* @param slc Address of the SLC registers
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*/
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static inline void sdio_slave_ll_send_stop(slc_dev_t *slc)
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{
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slc->slc0_rx_link.stop = 1;
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}
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/**
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* Enable the sending interrupt (rx_eof).
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*
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* @param slc Address of the SLC registers
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* @param ena true to enable, false to disable
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*/
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static inline void sdio_slave_ll_send_intr_ena(slc_dev_t *slc, bool ena)
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{
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slc->slc0_int_ena.rx_eof = (ena ? 1 : 0);
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}
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/**
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* Clear the sending interrupt (rx_eof).
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*
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* @param slc Address of the SLC registers
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*/
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static inline void sdio_slave_ll_send_intr_clr(slc_dev_t *slc)
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{
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slc->slc0_int_clr.rx_eof = 1;
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}
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/**
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* Check whether the sending is done.
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*
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* @param slc Address of the SLC registers
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* @return true if done, otherwise false
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*/
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static inline bool sdio_slave_ll_send_done(slc_dev_t *slc)
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{
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return slc->slc0_int_st.rx_eof != 0;
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}
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/**
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* Clear the host interrupt indicating the slave having packet to be read.
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*
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* @param host Address of the host registers
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*/
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static inline void sdio_slave_ll_send_hostint_clr(host_dev_t *host)
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{
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host->slc0_int_clr.rx_new_packet = 1;
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}
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/*---------------------------------------------------------------------------
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* Receive
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*--------------------------------------------------------------------------*/
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/**
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* Enable the receiving interrupt.
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*
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* @param slc Address of the SLC registers
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* @param ena
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*/
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static inline void sdio_slave_ll_recv_intr_ena(slc_dev_t *slc, bool ena)
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{
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slc->slc0_int_ena.tx_done = (ena ? 1 : 0);
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}
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/**
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* Start receiving DMA with the given descriptor.
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*
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* @param slc Address of the SLC registers
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* @param desc Descriptor of the receiving buffer.
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*/
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static inline void sdio_slave_ll_recv_start(slc_dev_t *slc, sdio_slave_ll_desc_t *desc)
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{
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slc->slc0_tx_link.addr = (uint32_t)desc;
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slc->slc0_tx_link.start = 1;
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}
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/**
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* Increase the receiving buffer counter by 1.
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*
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* @param slc Address of the SLC registers
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*/
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static inline void sdio_slave_ll_recv_size_inc(slc_dev_t *slc)
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{
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// fields wdata and inc_more should be written by the same instruction.
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slc->slc0_token1.val = FIELD_TO_VALUE2(SLC_SLC0_TOKEN1_WDATA, 1) | FIELD_TO_VALUE2(SLC_SLC0_TOKEN1_INC_MORE, 1);
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}
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/**
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* Reset the receiving buffer.
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*
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* @param slc Address of the SLC registers
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*/
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static inline void sdio_slave_ll_recv_size_reset(slc_dev_t *slc)
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{
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slc->slc0_token1.val = FIELD_TO_VALUE2(SLC_SLC0_TOKEN1_WDATA, 0) | FIELD_TO_VALUE2(SLC_SLC0_TOKEN1_WR, 1);
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}
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/**
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* Check whether there is a receiving finished event.
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*
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* @param slc Address of the SLC registers
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* @return
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*/
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static inline bool sdio_slave_ll_recv_done(slc_dev_t *slc)
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{
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return slc->slc0_int_raw.tx_done != 0;
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}
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/**
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* Clear the receiving finished interrupt.
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*
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* @param slc Address of the SLC registers
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*/
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static inline void sdio_slave_ll_recv_done_clear(slc_dev_t *slc)
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{
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slc->slc0_int_clr.tx_done = 1;
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}
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/**
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* Restart the DMA. Call after you modified the next pointer of the tail descriptor to the appended
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* descriptor.
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*
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* @param slc Address of the SLC registers
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*/
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static inline void sdio_slave_ll_recv_restart(slc_dev_t *slc)
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{
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slc->slc0_tx_link.restart = 1;
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}
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/**
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* Reset the receiving DMA.
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*
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* @param slc Address of the SLC registers
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*/
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static inline void sdio_slave_ll_recv_reset(slc_dev_t *slc)
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{
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slc->conf0.slc0_tx_rst = 1;
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slc->conf0.slc0_tx_rst = 0;
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}
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/**
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* Stop the receiving DMA.
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*
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* @param slc Address of the SLC registers
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*/
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static inline void sdio_slave_ll_recv_stop(slc_dev_t *slc)
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{
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slc->slc0_tx_link.stop = 1;
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}
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/*---------------------------------------------------------------------------
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* Host
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*--------------------------------------------------------------------------*/
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/**
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* Get the address of the shared general purpose register. Internal.
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*
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* @param host Address of the host registers
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* @param pos Position of the register, 0-63 except 24-27.
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* @return address of the register.
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*/
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static inline intptr_t sdio_slave_ll_host_get_w_reg(host_dev_t *host, int pos)
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{
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return (intptr_t) & (host->conf_w0) + pos + (pos > 23 ? 4 : 0) + (pos > 31 ? 12 : 0);
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}
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/**
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* Get the value of the shared general purpose register.
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*
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* @param host Address of the host registers
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* @param pos Position of the register, 0-63, except 24-27.
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* @return value of the register.
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*/
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static inline uint8_t sdio_slave_ll_host_get_reg(host_dev_t *host, int pos)
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{
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return *(uint8_t *)sdio_slave_ll_host_get_w_reg(host, pos);
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}
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/**
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* Set the value of the shared general purpose register.
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*
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* @param host Address of the host registers
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* @param pos Position of the register, 0-63, except 24-27.
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* @param reg Value to set.
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*/
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static inline void sdio_slave_ll_host_set_reg(host_dev_t *host, int pos, uint8_t reg)
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{
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uint32_t *addr = (uint32_t *)(sdio_slave_ll_host_get_w_reg(host, pos) & (~3));
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uint32_t shift = (pos % 4) * 8;
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*addr &= ~(0xff << shift);
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*addr |= ((uint32_t)reg << shift);
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}
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/**
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* Get the interrupt enable bits for the host.
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*
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* @param host Address of the host registers
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* @return Enabled interrupts
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*/
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static inline sdio_slave_hostint_t sdio_slave_ll_host_get_intena(host_dev_t *host)
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{
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return (sdio_slave_hostint_t)host->slc0_func1_int_ena.val;
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|
}
|
|
|
|
/**
|
|
* Set the interrupt enable bits for the host.
|
|
*
|
|
* @param host Address of the host registers
|
|
* @param mask Mask of interrupts to enable
|
|
*/
|
|
static inline void sdio_slave_ll_host_set_intena(host_dev_t *host, const sdio_slave_hostint_t *mask)
|
|
{
|
|
host->slc0_func1_int_ena.val = (*mask);
|
|
}
|
|
|
|
/**
|
|
* Clear the interrupt bits for the host.
|
|
* @param host Address of the host registers
|
|
* @param mask Mask of interrupts to clear.
|
|
*/
|
|
static inline void sdio_slave_ll_host_intr_clear(host_dev_t *host, const sdio_slave_hostint_t *mask)
|
|
{
|
|
host->slc0_int_clr.val = (*mask);
|
|
}
|
|
|
|
/**
|
|
* Send general purpose interrupts to the host.
|
|
* @param slc Address of the SLC registers
|
|
* @param mask Mask of interrupts to seend to host
|
|
*/
|
|
static inline void sdio_slave_ll_host_send_int(slc_dev_t *slc, const sdio_slave_hostint_t *mask)
|
|
{
|
|
//use registers in SLC to trigger, rather than write HOST registers directly
|
|
//other interrupts than tohost interrupts are not supported yet
|
|
slc->intvec_tohost.slc0_intvec = (*mask);
|
|
}
|
|
|
|
/**
|
|
* Enable some of the slave interrupts (send from host)
|
|
*
|
|
* @param slc Address of the SLC registers
|
|
* @param mask Mask of interrupts to enable, all those set to 0 will be disabled.
|
|
*/
|
|
static inline void sdio_slave_ll_slvint_set_ena(slc_dev_t *slc, const sdio_slave_ll_slvint_t *mask)
|
|
{
|
|
//other interrupts are not enabled
|
|
slc->slc0_int_ena.val = (slc->slc0_int_ena.val & (~0xff)) | ((*mask) & 0xff);
|
|
}
|
|
|
|
/**
|
|
* Fetch the slave interrupts (send from host) and clear them.
|
|
*
|
|
* @param slc Address of the SLC registers
|
|
* @param out_slv_int Output of the slave interrupts fetched and cleared.
|
|
*/
|
|
static inline void sdio_slave_ll_slvint_fetch_clear(slc_dev_t *slc, sdio_slave_ll_slvint_t *out_slv_int)
|
|
{
|
|
sdio_slave_ll_slvint_t slv_int = (sdio_slave_ll_slvint_t)(slc->slc0_int_st.val & 0xff);
|
|
*out_slv_int = slv_int;
|
|
slc->slc0_int_clr.val = slv_int;
|
|
}
|
|
|
|
#ifdef __cplusplus
|
|
}
|
|
#endif
|