kopia lustrzana https://github.com/espressif/esp-idf
166 wiersze
5.4 KiB
C
166 wiersze
5.4 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <stdlib.h>
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#include "hal/spi_flash_hal.h"
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#include "string.h"
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#include "hal/hal_defs.h"
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#define ADDRESS_MASK_24BIT 0xFFFFFF
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static inline spi_dev_t *get_spi_dev(spi_flash_host_driver_t *host)
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{
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return ((spi_flash_memspi_data_t *)host->driver_data)->spi;
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}
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void spi_flash_hal_poll_cmd_done(spi_flash_host_driver_t *host)
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{
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while (!spi_flash_ll_cmd_is_done(get_spi_dev(host))) {
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//nop
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}
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}
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esp_err_t spi_flash_hal_device_config(spi_flash_host_driver_t *host)
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{
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spi_flash_memspi_data_t *drv_data = (spi_flash_memspi_data_t *)host->driver_data;
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spi_dev_t *dev = get_spi_dev(host);
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spi_flash_ll_reset(dev);
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spi_flash_ll_set_cs_pin(dev, drv_data->cs_num);
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spi_flash_ll_set_clock(dev, &drv_data->clock_conf);
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spi_flash_ll_set_cs_setup(dev, 1);
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/*
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* workaround for the ROM: the ROM, as well as the OpenOCD, don't know the
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* clock registers and the dummy are modified this help the ROM to read and
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* write correctly according to the new dummy len.
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*/
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if (dev == &SPI1) {
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//0 for cache, 1 for SPI1
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extern uint8_t g_rom_spiflash_dummy_len_plus[];
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g_rom_spiflash_dummy_len_plus[1] = drv_data->extra_dummy;
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}
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return ESP_OK;
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}
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esp_err_t spi_flash_hal_configure_host_io_mode(
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spi_flash_host_driver_t *host,
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uint32_t command,
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uint32_t addr_bitlen,
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int dummy_cyclelen_base,
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esp_flash_io_mode_t io_mode)
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{
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// Add dummy cycles to compensate for latency of GPIO matrix and external delay, if necessary...
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int dummy_cyclelen = dummy_cyclelen_base + ((spi_flash_memspi_data_t *)host->driver_data)->extra_dummy;
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spi_dev_t *dev = get_spi_dev(host);
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spi_flash_ll_set_command8(dev, command);
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spi_flash_ll_set_addr_bitlen(dev, addr_bitlen);
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spi_flash_ll_set_dummy(dev, dummy_cyclelen);
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//disable all data phases, enable them later if needed
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spi_flash_ll_set_miso_bitlen(dev, 0);
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spi_flash_ll_set_mosi_bitlen(dev, 0);
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spi_flash_ll_set_read_mode(dev, io_mode);
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return ESP_OK;
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}
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esp_err_t spi_flash_hal_common_command(spi_flash_host_driver_t *host, spi_flash_trans_t *trans)
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{
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host->configure_host_io_mode(host, trans->command, 0, 0, SPI_FLASH_FASTRD);
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spi_dev_t *dev = get_spi_dev(host);
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//disable dummy if no input phase
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if (trans->miso_len == 0) {
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spi_flash_ll_set_dummy(dev, 0);
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}
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spi_flash_ll_set_miso_bitlen(dev, trans->miso_len);
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spi_flash_ll_set_mosi_bitlen(dev, trans->mosi_len);
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spi_flash_ll_write_word(dev, trans->mosi_data);
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spi_flash_ll_user_start(dev);
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host->poll_cmd_done(host);
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spi_flash_ll_get_buffer_data(dev, trans->miso_data, 8);
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return ESP_OK;
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}
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void spi_flash_hal_erase_chip(spi_flash_host_driver_t *host)
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{
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spi_dev_t *dev = get_spi_dev(host);
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spi_flash_ll_erase_chip(dev);
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host->poll_cmd_done(host);
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}
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void spi_flash_hal_erase_sector(spi_flash_host_driver_t *host, uint32_t start_address)
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{
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spi_dev_t *dev = get_spi_dev(host);
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spi_flash_ll_set_addr_bitlen(dev, 24);
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spi_flash_ll_set_address(dev, start_address & ADDRESS_MASK_24BIT);
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spi_flash_ll_erase_sector(dev);
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host->poll_cmd_done(host);
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}
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void spi_flash_hal_erase_block(spi_flash_host_driver_t *host, uint32_t start_address)
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{
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spi_dev_t *dev = get_spi_dev(host);
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spi_flash_ll_set_addr_bitlen(dev, 24);
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spi_flash_ll_set_address(dev, start_address & ADDRESS_MASK_24BIT);
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spi_flash_ll_erase_block(dev);
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host->poll_cmd_done(host);
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}
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void spi_flash_hal_program_page(spi_flash_host_driver_t *host, const void *buffer, uint32_t address, uint32_t length)
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{
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spi_dev_t *dev = get_spi_dev(host);
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spi_flash_ll_set_addr_bitlen(dev, 24);
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spi_flash_ll_set_address(dev, (address & ADDRESS_MASK_24BIT) | (length << 24));
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spi_flash_ll_program_page(dev, buffer, length);
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host->poll_cmd_done(host);
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}
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esp_err_t spi_flash_hal_read(spi_flash_host_driver_t *host, void *buffer, uint32_t address, uint32_t read_len)
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{
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spi_dev_t *dev = get_spi_dev(host);
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//the command is already set by ``spi_flash_hal_configure_host_io_mode`` before.
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spi_flash_ll_set_address(dev, address << 8);
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spi_flash_ll_set_miso_bitlen(dev, read_len * 8);
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spi_flash_ll_user_start(dev);
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host->poll_cmd_done(host);
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spi_flash_ll_get_buffer_data(dev, buffer, read_len);
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return ESP_OK;
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}
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bool spi_flash_hal_host_idle(spi_flash_host_driver_t *host)
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{
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spi_dev_t *dev = get_spi_dev(host);
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bool idle = spi_flash_ll_host_idle(dev);
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// Not clear if this is necessary, or only necessary if
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// chip->spi == SPI1. But probably doesn't hurt...
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if (dev == &SPI1) {
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idle &= spi_flash_ll_host_idle(&SPI0);
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}
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return idle;
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}
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esp_err_t spi_flash_hal_set_write_protect(spi_flash_host_driver_t *host, bool wp)
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{
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spi_dev_t *dev = get_spi_dev(host);
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spi_flash_ll_set_write_protect(dev, wp);
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host->poll_cmd_done(host);
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return ESP_OK;
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}
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