esp-idf/components/esp32s3
Angus Gratton 420aef1ffe Updates for riscv support
* Target components pull in xtensa component directly
* Use CPU HAL where applicable
* Remove unnecessary xtensa headers
* Compilation changes necessary to support non-xtensa gcc types (ie int32_t/uint32_t is no
  longer signed/unsigned int).

Changes come from internal branch commit a6723fc
2020-11-13 07:49:11 +11:00
..
include Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
ld
CMakeLists.txt Updates for riscv support 2020-11-13 07:49:11 +11:00
Kconfig Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
Makefile.projbuild
README.md
cache_err_int.c
clk.c Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
component.mk
crosscore_int.c
dport_access.c
esp_crypto_lock.c Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
hw_random.c
linker.lf
memprot.c
spiram.c
spiram_psram.c Whitespace: Automated whitespace fixes (large commit) 2020-11-11 07:36:35 +00:00
spiram_psram.h
system_api_esp32s3.c

README.md

ESP32-S3 component

This directory contains support for the upcoming ESP32-S3 SoC. This code is still work in progress and not intended for public use.

Please follow announcements on espressif.com and esp32.com to be informed about the ESP32-S3 SoC.

This note will be removed once the ESP32-S3 initial support is ready.