kopia lustrzana https://github.com/espressif/esp-idf
109 wiersze
4.2 KiB
C
109 wiersze
4.2 KiB
C
// Copyright 2020 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "freertos/FreeRTOS.h"
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#include "soc/periph_defs.h"
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#include "soc/soc_memory_layout.h"
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#include "soc/soc_caps.h"
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#include "hal/gdma_ll.h"
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#include "hal/gdma_hal.h"
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#include "driver/periph_ctrl.h"
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#include "esp_log.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_async_memcpy_impl.h"
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IRAM_ATTR static void async_memcpy_impl_default_isr_handler(void *args)
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{
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async_memcpy_impl_t *mcp_impl = (async_memcpy_impl_t *)args;
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portENTER_CRITICAL_ISR(&mcp_impl->hal_lock);
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uint32_t status = gdma_ll_get_interrupt_status(mcp_impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL);
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gdma_ll_clear_interrupt_status(mcp_impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, status);
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portEXIT_CRITICAL_ISR(&mcp_impl->hal_lock);
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// End-Of-Frame on RX side
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if (status & GDMA_LL_EVENT_RX_SUC_EOF) {
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async_memcpy_isr_on_rx_done_event(mcp_impl);
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}
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if (mcp_impl->isr_need_yield) {
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mcp_impl->isr_need_yield = false;
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portYIELD_FROM_ISR();
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}
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}
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esp_err_t async_memcpy_impl_allocate_intr(async_memcpy_impl_t *impl, int int_flags, intr_handle_t *intr)
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{
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return esp_intr_alloc(ETS_DMA_CH0_INTR_SOURCE, int_flags, async_memcpy_impl_default_isr_handler, impl, intr);
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}
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esp_err_t async_memcpy_impl_init(async_memcpy_impl_t *impl, dma_descriptor_t *outlink_base, dma_descriptor_t *inlink_base)
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{
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impl->hal_lock = (portMUX_TYPE)portMUX_INITIALIZER_UNLOCKED;
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impl->hal.dev = &GDMA;
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periph_module_enable(PERIPH_GDMA_MODULE);
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gdma_ll_enable_clock(impl->hal.dev, true);
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gdma_ll_tx_reset_channel(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL);
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gdma_ll_rx_reset_channel(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL);
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gdma_ll_enable_interrupt(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, UINT32_MAX, true);
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gdma_ll_clear_interrupt_status(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, UINT32_MAX);
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gdma_ll_enable_m2m_mode(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, true);
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gdma_ll_tx_enable_auto_write_back(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, true);
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gdma_ll_tx_enable_owner_check(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, true);
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gdma_ll_rx_enable_owner_check(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, true);
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gdma_ll_tx_set_desc_addr(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, (uint32_t)outlink_base);
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gdma_ll_rx_set_desc_addr(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, (uint32_t)inlink_base);
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return ESP_OK;
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}
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esp_err_t async_memcpy_impl_deinit(async_memcpy_impl_t *impl)
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{
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periph_module_disable(PERIPH_GDMA_MODULE);
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return ESP_OK;
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}
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esp_err_t async_memcpy_impl_start(async_memcpy_impl_t *impl)
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{
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gdma_ll_rx_start(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL);
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gdma_ll_tx_start(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL);
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gdma_ll_enable_interrupt(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, GDMA_LL_EVENT_RX_SUC_EOF, true);
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return ESP_OK;
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}
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esp_err_t async_memcpy_impl_stop(async_memcpy_impl_t *impl)
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{
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gdma_ll_enable_interrupt(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL, GDMA_LL_EVENT_RX_SUC_EOF, false);
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gdma_ll_rx_stop(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL);
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gdma_ll_tx_stop(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL);
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return ESP_OK;
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}
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esp_err_t async_memcpy_impl_restart(async_memcpy_impl_t *impl)
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{
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gdma_ll_rx_restart(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL);
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gdma_ll_tx_restart(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL);
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return ESP_OK;
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}
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bool async_memcpy_impl_is_buffer_address_valid(async_memcpy_impl_t *impl, void *src, void *dst)
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{
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return true;
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}
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dma_descriptor_t *async_memcpy_impl_get_rx_suc_eof_descriptor(async_memcpy_impl_t *impl)
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{
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return (dma_descriptor_t *)gdma_ll_rx_get_success_eof_desc_addr(impl->hal.dev, SOC_GDMA_M2M_DMA_CHANNEL);
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}
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