kopia lustrzana https://github.com/espressif/esp-idf
210 wiersze
8.0 KiB
C
210 wiersze
8.0 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "esp_rom_sys.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/rtc_cntl_ll.h"
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#include "hal/timer_ll.h"
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#include "soc/rtc.h"
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#include "soc/timer_periph.h"
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#include "esp_hw_log.h"
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#include "esp_private/periph_ctrl.h"
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static const char *TAG = "rtc_time";
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/* Calibration of RTC_SLOW_CLK is performed using a special feature of TIMG0.
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* This feature counts the number of XTAL clock cycles within a given number of
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* RTC_SLOW_CLK cycles.
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*
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* Slow clock calibration feature has two modes of operation: one-off and cycling.
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* In cycling mode (which is enabled by default on SoC reset), counting of XTAL
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* cycles within RTC_SLOW_CLK cycle is done continuously. Cycling mode is enabled
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* using TIMG_RTC_CALI_START_CYCLING bit. In one-off mode counting is performed
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* once, and TIMG_RTC_CALI_RDY bit is set when counting is done. One-off mode is
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* enabled using TIMG_RTC_CALI_START bit.
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*/
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/**
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* @brief Clock calibration function used by rtc_clk_cal and rtc_clk_cal_ratio
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* @param cal_clk which clock to calibrate
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* @param slowclk_cycles number of slow clock cycles to count. Max value is 32766.
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* @return number of XTAL clock cycles within the given number of slow clock cycles
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*/
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static uint32_t rtc_clk_cal_internal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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{
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assert(slowclk_cycles < 32767);
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/* Enable requested clock (150k clock is always on) */
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bool dig_32k_xtal_enabled = clk_ll_xtal32k_digi_is_enabled();
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if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
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clk_ll_xtal32k_digi_enable();
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}
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bool rc_fast_enabled = clk_ll_rc_fast_is_enabled();
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bool rc_fast_d256_enabled = clk_ll_rc_fast_d256_is_enabled();
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if (cal_clk == RTC_CAL_8MD256) {
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rtc_clk_8m_enable(true, true);
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clk_ll_rc_fast_d256_digi_enable();
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}
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/* Prepare calibration */
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, cal_clk);
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING);
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, slowclk_cycles);
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/* Figure out how long to wait for calibration to finish */
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uint32_t expected_freq;
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soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
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if (cal_clk == RTC_CAL_32K_XTAL ||
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(cal_clk == RTC_CAL_RTC_MUX && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K)) {
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expected_freq = SOC_CLK_XTAL32K_FREQ_APPROX; /* standard 32k XTAL */
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} else if (cal_clk == RTC_CAL_8MD256 ||
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(cal_clk == RTC_CAL_RTC_MUX && slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256)) {
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expected_freq = SOC_CLK_RC_FAST_D256_FREQ_APPROX;
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} else {
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expected_freq = SOC_CLK_RC_SLOW_FREQ_APPROX; /* 150k internal oscillator */
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}
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uint32_t us_time_estimate = (uint32_t) (((uint64_t) slowclk_cycles) * MHZ / expected_freq);
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/* Check if the required number of slowclk_cycles may result in an overflow of TIMG_RTC_CALI_VALUE */
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soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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if (xtal_freq == SOC_XTAL_FREQ_AUTO) {
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/* XTAL frequency is not known yet; assume worst case (40 MHz) */
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xtal_freq = SOC_XTAL_FREQ_40M;
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}
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const uint32_t us_timer_max = TIMG_RTC_CALI_VALUE / (uint32_t) xtal_freq;
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if (us_time_estimate >= us_timer_max) {
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ESP_HW_LOGE(TAG, "slowclk_cycles value too large, possible overflow");
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return 0;
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}
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/* Start calibration */
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CLEAR_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
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SET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
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/* Wait the expected time calibration should take.
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* TODO: if running under RTOS, and us_time_estimate > RTOS tick, use the
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* RTOS delay function.
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*/
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esp_rom_delay_us(us_time_estimate);
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/* Wait for calibration to finish up to another us_time_estimate */
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int timeout_us = us_time_estimate;
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while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY) &&
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timeout_us > 0) {
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timeout_us--;
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esp_rom_delay_us(1);
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}
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/* if dig_32k_xtal was originally off and enabled due to calibration, then set back to off state */
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if (cal_clk == RTC_CAL_32K_XTAL && !dig_32k_xtal_enabled) {
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clk_ll_xtal32k_digi_disable();
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}
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if (cal_clk == RTC_CAL_8MD256) {
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clk_ll_rc_fast_d256_digi_disable();
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rtc_clk_8m_enable(rc_fast_enabled, rc_fast_d256_enabled);
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}
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if (timeout_us == 0) {
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/* timed out waiting for calibration */
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return 0;
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}
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return REG_GET_FIELD(TIMG_RTCCALICFG1_REG(0), TIMG_RTC_CALI_VALUE);
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}
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uint32_t rtc_clk_cal_ratio(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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{
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assert(slowclk_cycles);
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uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
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uint64_t ratio_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT)) / slowclk_cycles;
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uint32_t ratio = (uint32_t)(ratio_64 & UINT32_MAX);
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return ratio;
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}
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static inline bool rtc_clk_cal_32k_valid(uint32_t xtal_freq, uint32_t slowclk_cycles, uint64_t actual_xtal_cycles)
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{
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uint64_t expected_xtal_cycles = (xtal_freq * 1000000ULL * slowclk_cycles) >> 15; // xtal_freq(hz) * slowclk_cycles / 32768
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uint64_t delta = expected_xtal_cycles / 2000; // 5/10000
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return (actual_xtal_cycles >= (expected_xtal_cycles - delta)) && (actual_xtal_cycles <= (expected_xtal_cycles + delta));
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}
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uint32_t rtc_clk_cal(rtc_cal_sel_t cal_clk, uint32_t slowclk_cycles)
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{
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assert(slowclk_cycles);
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soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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uint64_t xtal_cycles = rtc_clk_cal_internal(cal_clk, slowclk_cycles);
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if ((cal_clk == RTC_CAL_32K_XTAL) && !rtc_clk_cal_32k_valid((uint32_t)xtal_freq, slowclk_cycles, xtal_cycles)) {
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return 0;
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}
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uint64_t divider = ((uint64_t)xtal_freq) * slowclk_cycles;
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uint64_t period_64 = ((xtal_cycles << RTC_CLK_CAL_FRACT) + divider / 2 - 1) / divider;
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uint32_t period = (uint32_t)(period_64 & UINT32_MAX);
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return period;
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}
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uint64_t rtc_time_us_to_slowclk(uint64_t time_in_us, uint32_t period)
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{
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assert(period);
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/* Overflow will happen in this function if time_in_us >= 2^45, which is about 400 days.
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* TODO: fix overflow.
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*/
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return (time_in_us << RTC_CLK_CAL_FRACT) / period;
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}
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uint64_t rtc_time_slowclk_to_us(uint64_t rtc_cycles, uint32_t period)
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{
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return (rtc_cycles * period) >> RTC_CLK_CAL_FRACT;
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}
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uint64_t rtc_time_get(void)
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{
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return rtc_cntl_ll_get_rtc_time();
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}
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void rtc_clk_wait_for_slow_cycle(void)
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{
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REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START_CYCLING | TIMG_RTC_CALI_START);
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REG_CLR_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY);
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_CLK_SEL, RTC_CAL_RTC_MUX);
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/* Request to run calibration for 0 slow clock cycles.
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* RDY bit will be set on the nearest slow clock cycle.
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*/
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REG_SET_FIELD(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_MAX, 0);
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REG_SET_BIT(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_START);
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esp_rom_delay_us(1); /* RDY needs some time to go low */
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int attempts = 1000;
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while (!GET_PERI_REG_MASK(TIMG_RTCCALICFG_REG(0), TIMG_RTC_CALI_RDY)) {
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esp_rom_delay_us(1);
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if (attempts) {
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if (--attempts == 0 && clk_ll_xtal32k_digi_is_enabled()) {
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ESP_HW_LOGE(TAG, "32kHz xtal has been stopped");
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}
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}
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}
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}
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uint32_t rtc_clk_freq_cal(uint32_t cal_val)
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{
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if (cal_val == 0) {
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return 0; // cal_val will be denominator, return 0 as the symbol of failure.
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}
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return 1000000ULL * (1 << RTC_CLK_CAL_FRACT) / cal_val;
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}
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/// @brief if the calibration is used, we need to enable the timer group0 first
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__attribute__((constructor))
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static void enable_timer_group0_for_calibration(void)
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{
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#ifndef BOOTLOADER_BUILD
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PERIPH_RCC_ACQUIRE_ATOMIC(PERIPH_TIMG0_MODULE, ref_count) {
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if (ref_count == 0) {
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timer_ll_enable_bus_clock(0, true);
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timer_ll_reset_register(0);
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}
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}
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#else
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_timer_ll_enable_bus_clock(0, true);
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_timer_ll_reset_register(0);
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#endif
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}
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