kopia lustrzana https://github.com/espressif/esp-idf
2d37bfa126
- add lock for single read and continuous read APIs - update onetime read start singal delay for hardware limitation[*] - move adc_caps to soc_caps.h - update license dates [*] There is a hardware limitation. If the APB clock frequency is high, the step of this reg signal: ``onetime_start`` may not be captured by the ADC digital controller (when its clock frequency is too slow). A rough estimate for this step should be at least 3 ADC digital controller clock cycle. |
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| .. | ||
| include/driver | ||
| adc.c | ||