kopia lustrzana https://github.com/espressif/esp-idf
146 wiersze
4.9 KiB
C
146 wiersze
4.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// HAL for SPI Flash (non-IRAM part)
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// The IRAM part is in spi_flash_hal_iram.c, spi_flash_hal_gpspi.c, spi_flash_hal_common.inc.
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#include <stdlib.h>
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#include <string.h>
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#include "soc/soc_caps.h"
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#include "hal/spi_flash_hal.h"
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#define APB_CYCLE_NS (1000*1000*1000LL/APB_CLK_FREQ)
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typedef struct {
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int div;
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spi_flash_ll_clock_reg_t clock_reg_val;
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} spi_flash_hal_clock_config_t;
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static const spi_flash_hal_clock_config_t spi_flash_clk_cfg_reg[ESP_FLASH_SPEED_MAX] = {
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{16, SPI_FLASH_LL_CLKREG_VAL_5MHZ},
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{8, SPI_FLASH_LL_CLKREG_VAL_10MHZ},
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{4, SPI_FLASH_LL_CLKREG_VAL_20MHZ},
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{3, SPI_FLASH_LL_CLKREG_VAL_26MHZ},
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{2, SPI_FLASH_LL_CLKREG_VAL_40MHZ},
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{1, SPI_FLASH_LL_CLKREG_VAL_80MHZ},
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};
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#if !CONFIG_IDF_TARGET_ESP32
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static const spi_flash_hal_clock_config_t spi_flash_gpspi_clk_cfg_reg[ESP_FLASH_SPEED_MAX] = {
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{16, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_5MHZ}},
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{8, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_10MHZ}},
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{4, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_20MHZ}},
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{3, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_26MHZ}},
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{2, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_40MHZ}},
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{1, {.gpspi=GPSPI_FLASH_LL_CLKREG_VAL_80MHZ}},
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};
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#else
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#define spi_flash_gpspi_clk_cfg_reg spi_flash_clk_cfg_reg
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#endif
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static inline int get_dummy_n(bool gpio_is_used, int input_delay_ns, int eff_clk)
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{
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const int apbclk_kHz = APB_CLK_FREQ / 1000;
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//calculate how many apb clocks a period has
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const int apbclk_n = APB_CLK_FREQ / eff_clk;
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const int gpio_delay_ns = gpio_is_used ? GPIO_MATRIX_DELAY_NS : 0;
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//calculate how many apb clocks the delay is, the 1 is to compensate in case ``input_delay_ns`` is rounded off.
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int apb_period_n = (1 + input_delay_ns + gpio_delay_ns) * apbclk_kHz / 1000 / 1000;
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if (apb_period_n < 0) {
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apb_period_n = 0;
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}
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return apb_period_n / apbclk_n;
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}
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#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
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static inline int extra_dummy_under_timing_tuning(const spi_flash_hal_config_t *cfg)
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{
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bool main_flash = (cfg->host_id == SPI1_HOST && cfg->cs_num == 0);
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int extra_dummy = 0;
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if (main_flash) {
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/**
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* For Octal Flash, the dummy is `usr_dummy` + `extra_dummy`, they are in two different regs, we don't touch `extra_dummy` here, so set extra_dummy 0.
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* Instead, for both Quad and Octal Flash, we use `usr_dummy` and set the whole dummy length (usr_dummy + extra_dummy) to this register.
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*/
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extra_dummy = cfg->extra_dummy;
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} else {
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// TODO: for other flash chips, dummy get logic implement here. Currently, still calculate extra dummy by itself.
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abort();
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}
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return extra_dummy;
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}
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#endif //SOC_SPI_MEM_SUPPORT_TIME_TUNING
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esp_err_t spi_flash_hal_init(spi_flash_hal_context_t *data_out, const spi_flash_hal_config_t *cfg)
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{
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if (cfg->cs_num >= SOC_SPI_PERIPH_CS_NUM(cfg->host_id)) {
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return ESP_ERR_INVALID_ARG;
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}
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bool gpspi = (cfg->host_id > SPI1_HOST);
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const spi_flash_hal_clock_config_t *clock_cfg = gpspi? &spi_flash_gpspi_clk_cfg_reg[cfg->speed]: &spi_flash_clk_cfg_reg[cfg->speed];
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*data_out = (spi_flash_hal_context_t) {
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.inst = data_out->inst, // Keeps the function pointer table
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.spi = spi_flash_ll_get_hw(cfg->host_id),
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.cs_num = cfg->cs_num,
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.cs_hold = cfg->cs_hold,
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.cs_setup = cfg->cs_setup,
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.base_io_mode = cfg->default_io_mode,
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};
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#if SOC_SPI_MEM_SUPPORT_TIME_TUNING
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if (cfg->using_timing_tuning) {
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data_out->extra_dummy = extra_dummy_under_timing_tuning(cfg);
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data_out->clock_conf = cfg->clock_config;
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} else
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#endif // SOC_SPI_MEM_SUPPORT_TIME_TUNING
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{
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data_out->extra_dummy = get_dummy_n(!cfg->iomux, cfg->input_delay_ns, APB_CLK_FREQ/clock_cfg->div);
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data_out->clock_conf = clock_cfg->clock_reg_val;
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}
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if (cfg->auto_sus_en) {
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data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_SUSPEND;
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data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_AUTO_RESUME;
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}
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#if SOC_SPI_MEM_SUPPORT_OPI_MODE
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if (cfg->octal_mode_en) {
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data_out->flags |= SPI_FLASH_HOST_CONTEXT_FLAG_OCTAL_MODE;
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}
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if (cfg->default_io_mode == SPI_FLASH_OPI_DTR) {
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data_out->slicer_flags |= SPI_FLASH_HOST_CONTEXT_SLICER_FLAG_DTR;
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}
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#endif
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return ESP_OK;
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}
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bool spi_flash_hal_supports_direct_write(spi_flash_host_inst_t *host, const void *p)
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{
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(void)p;
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bool direct_write = (((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI1_HOST));
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return direct_write;
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}
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bool spi_flash_hal_supports_direct_read(spi_flash_host_inst_t *host, const void *p)
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{
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(void)p;
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//currently the host doesn't support to read through dma, no word-aligned requirements
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bool direct_read = ( ((spi_flash_hal_context_t *)host)->spi != spi_flash_ll_get_hw(SPI1_HOST));
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return direct_read;
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}
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