kopia lustrzana https://github.com/espressif/esp-idf
186 wiersze
7.2 KiB
C
186 wiersze
7.2 KiB
C
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _SOC_CRYPTO_DMA_REG_H_
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#define _SOC_CRYPTO_DMA_REG_H_
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include "soc.h"
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/* CRYPTO_DMA_CONF0 : RO ;bitpos:[31:14] ;default: 18'h0 ; */
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/* CONF0_REG_GEN_CLK_EN : RW ;bitpos:[13] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_GEN_CLK_EN (BIT(13))
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#define CONF0_REG_GEN_CLK_EN_M (BIT(13))
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#define CONF0_REG_GEN_CLK_EN_V 0x1
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#define CONF0_REG_GEN_CLK_EN_S 13
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/* CONF0_REG_MEM_TRANS_EN: RW ;bitpos:[12] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_MEM_TRANS_EN (BIT(12))
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#define CONF0_REG_MEM_TRANS_EN_M (BIT(12))
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#define CONF0_REG_MEM_TRANS_EN_V 0x1
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#define CONF0_REG_MEM_TRANS_EN_S 12
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/* CONF0_REG_OUT_DATA_BURST_EN: RW ;bitpos:[11] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_OUT_DATA_BURST_EN (BIT(11))
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#define CONF0_REG_OUT_DATA_BURST_EN_M (BIT(11))
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#define CONF0_REG_OUT_DATA_BURST_EN_V 0x1
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#define CONF0_REG_OUT_DATA_BURST_EN_S 11
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/* CONF0_REG_INDSCR_BURST_EN: RW ;bitpos:[10] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_INDSCR_BURST_EN (BIT(10))
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#define CONF0_REG_INDSCR_BURST_EN_M (BIT(10))
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#define CONF0_REG_INDSCR_BURST_EN_V 0x1
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#define CONF0_REG_INDSCR_BURST_EN_S 10
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/* CONF0_REG_OUTDSCR_BURST_EN: RW ;bitpos:[9] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_OUTDSCR_BURST_EN (BIT(9))
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#define CONF0_REG_OUTDSCR_BURST_EN_M (BIT(9))
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#define CONF0_REG_OUTDSCR_BURST_EN_V 0x1
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#define CONF0_REG_OUTDSCR_BURST_EN_S 9
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/* CONF0_REG_OUT_EOF_MODE: RW ;bitpos:[8] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_OUT_EOF_MODE (BIT(8))
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#define CONF0_REG_OUT_EOF_MODE_M (BIT(8))
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#define CONF0_REG_OUT_EOF_MODE_V 0x1
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#define CONF0_REG_OUT_EOF_MODE_S 8
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/* CONF0_REG_OUT_NO_RESTART_CLR: RW ;bitpos:[7] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_OUT_NO_RESTART_CLR (BIT(7))
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#define CONF0_REG_OUT_NO_RESTART_CLR_M (BIT(7))
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#define CONF0_REG_OUT_NO_RESTART_CLR_V 0x1
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#define CONF0_REG_OUT_NO_RESTART_CLR_S 7
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/* CONF0_REG_OUT_AUTO_WRBACK: RW ;bitpos:[6] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_OUT_AUTO_WRBACK (BIT(6))
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#define CONF0_REG_OUT_AUTO_WRBACK_M (BIT(6))
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#define CONF0_REG_OUT_AUTO_WRBACK_V 0x1
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#define CONF0_REG_OUT_AUTO_WRBACK_S 6
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/* CONF0_REG_OUT_LOOP_TEST: RW ;bitpos:[5] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_OUT_LOOP_TEST (BIT(5))
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#define CONF0_REG_OUT_LOOP_TEST_M (BIT(5))
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#define CONF0_REG_OUT_LOOP_TEST_V 0x1
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#define CONF0_REG_OUT_LOOP_TEST_S 5
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/* CONF0_REG_IN_LOOP_TEST: RW ;bitpos:[4] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_IN_LOOP_TEST (BIT(4))
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#define CONF0_REG_IN_LOOP_TEST_M (BIT(4))
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#define CONF0_REG_IN_LOOP_TEST_V 0x1
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#define CONF0_REG_IN_LOOP_TEST_S 4
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/* CONF0_REG_AHBM_RST: RW ;bitpos:[3] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_AHBM_RST (BIT(3))
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#define CONF0_REG_AHBM_RST_M (BIT(3))
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#define CONF0_REG_AHBM_RST_V 0x1
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#define CONF0_REG_AHBM_RST_S 3
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/* CONF0_REG_AHBM_FIFO_RST: RW ;bitpos:[2] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_AHBM_FIFO_RST (BIT(2))
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#define CONF0_REG_AHBM_FIFO_RST_M (BIT(2))
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#define CONF0_REG_AHBM_FIFO_RST_V 0x1
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#define CONF0_REG_AHBM_FIFO_RST_S 2
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/* CONF0_REG_OUT_RST: RW ;bitpos:[1] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_OUT_RST (BIT(1))
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#define CONF0_REG_OUT_RST_M (BIT(1))
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#define CONF0_REG_OUT_RST_V 0x1
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#define CONF0_REG_OUT_RST_S 1
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/* CONF0_REG_IN_RST: RW ;bitpos:[0] ;default: 1'b0 ; */
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/*description: */
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#define CONF0_REG_IN_RST (BIT(0))
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#define CONF0_REG_IN_RST_M (BIT(0))
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#define CONF0_REG_IN_RST_V 0x1
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#define CONF0_REG_IN_RST_S 0
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/* CRYPTO_DMA_INT_RAW : RO ;bitpos:[31:10] ;default: 22'h0 ; */
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/* INT_RAW_OUT_TOTAL_EOF : RW ;bitpos:[8] ;default: 1'b0 ; */
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/*description: */
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#define INT_RAW_OUT_TOTAL_EOF ( BIT(8))
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#define INT_RAW_OUT_TOTAL_EOF_M (BIT(8))
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#define INT_RAW_OUT_TOTAL_EOF_V 0x1
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#define INT_RAW_OUT_TOTAL_EOF_S 8
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/* INT_RAW_IN_SUC_EOF : RW ;bitpos:[1] ;default: 1'b0 ; */
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/*description: */
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#define INT_RAW_IN_SUC_EOF ( BIT(1))
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#define INT_RAW_IN_SUC_EOF_M (BIT(1))
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#define INT_RAW_IN_SUC_EOF_V 0x1
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#define INT_RAW_IN_SUC_EOF_S 1
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/* CRYPTO_DMA_OUT_LINK : RO ;bitpos:[31] ;default: 1'h0 ; */
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/* OUT_LINK_REG_OUTLINK_RESTART : RW ;bitpos:[30] ;default: 1'b0 ; */
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/*description: */
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#define OUT_LINK_REG_OUTLINK_RESTART ( BIT(30))
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#define OUT_LINK_REG_OUTLINK_RESTART_M (BIT(30))
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#define OUT_LINK_REG_OUTLINK_RESTART_V 0x1
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#define OUT_LINK_REG_OUTLINK_RESTART_S 30
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/* OUT_LINK_REG_OUTLINK_START : RW ;bitpos:[29] ;default: 1'b0 ; */
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/*description: */
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#define OUT_LINK_REG_OUTLINK_START ( BIT(29))
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#define OUT_LINK_REG_OUTLINK_START_M (BIT(29))
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#define OUT_LINK_REG_OUTLINK_START_V 0x1
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#define OUT_LINK_REG_OUTLINK_START_S 29
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/* OUT_LINK_REG_OUTLINK_STOP : RW ;bitpos:[28] ;default: 1'b0 ; */
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/*description: */
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#define OUT_LINK_REG_OUTLINK_STOP ( BIT(28))
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#define OUT_LINK_REG_OUTLINK_STOP_M (BIT(28))
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#define OUT_LINK_REG_OUTLINK_STOP_V 0x1
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#define OUT_LINK_REG_OUTLINK_STOP_S 28
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/* OUT_LINK_REG_OUTLINK_ADDR : RW ;bitpos:[19:0] ;default: 20'h0 ; */
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/*description: */
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#define OUT_LINK_REG_OUTLINK_ADDR 0x000FFFFF
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#define OUT_LINK_REG_OUTLINK_ADDR_M (OUT_LINK_REG_OUTLINK_ADDR_V<<OUT_LINK_REG_OUTLINK_ADDR_S)
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#define OUT_LINK_REG_OUTLINK_ADDR_V 0xFFFFF
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#define OUT_LINK_REG_OUTLINK_ADDR_S 0
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/* CRYPTO_DMA_IN_LINK : RO ;bitpos:[31] ;default: 1'h0 ; */
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/* IN_LINK_REG_INLINK_RESTART : RW ;bitpos:[30] ;default: 1'b0 ; */
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/*description: */
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#define IN_LINK_REG_INLINK_RESTART ( BIT(30))
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#define IN_LINK_REG_INLINK_RESTART_M (BIT(30))
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#define IN_LINK_REG_INLINK_RESTART_V 0x1
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#define IN_LINK_REG_INLINK_RESTART_S 30
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/* IN_LINK_REG_INLINK_START : RW ;bitpos:[29] ;default: 1'b0 ; */
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/*description: */
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#define IN_LINK_REG_INLINK_START ( BIT(29))
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#define IN_LINK_REG_INLINK_START_M (BIT(29))
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#define IN_LINK_REG_INLINK_START_V 0x1
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#define IN_LINK_REG_INLINK_START_S 29
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/* IN_LINK_REG_INLINK_STOP : RW ;bitpos:[28] ;default: 1'b0 ; */
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/*description: */
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#define IN_LINK_REG_INLINK_STOP ( BIT(28))
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#define IN_LINK_REG_INLINK_STOP_M (BIT(28))
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#define IN_LINK_REG_INLINK_STOP_V 0x1
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#define IN_LINK_REG_INLINK_STOP_S 28
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/* IN_LINK_REG_INLINK_ADDR : RW ;bitpos:[19:0] ;default: 20'h0 ; */
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/*description: */
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#define IN_LINK_REG_INLINK_ADDR 0x000FFFFF
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#define IN_LINK_REG_INLINK_ADDR_M (IN_LINK_REG_INLINK_ADDR_V<<IN_LINK_REG_INLINK_ADDR_S)
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#define IN_LINK_REG_INLINK_ADDR_V 0xFFFFF
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#define IN_LINK_REG_INLINK_ADDR_S 0
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/* CRYPTO_DMA_AES_SHA_SELECT : RO ;bitpos:[31:1] ;default: 31'b0 ; */
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/* AES_SHA_SELECT : RW ;bitpos:[0] ;default: 1'b0 ; */
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/*description: */
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#define AES_SHA_SELECT ( BIT(0))
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#define AES_SHA_SELECT_M (BIT(0))
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#define AES_SHA_SELECT_V 0x1
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#define AES_SHA_SELECT_S 0
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#ifdef __cplusplus
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}
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#endif
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#endif /*_SOC_CRYPTO_DMA_REG_H_ */
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