kopia lustrzana https://github.com/espressif/esp-idf
139 wiersze
5.1 KiB
C
139 wiersze
5.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include "esp_bit_defs.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/*IRAM0 is connected with Cache IBUS0*/
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#define SOC_IRAM0_ADDRESS_LOW 0x4037C000
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#define SOC_IRAM0_ADDRESS_HIGH 0x403E0000
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#define SOC_IRAM0_CACHE_ADDRESS_LOW 0x42000000
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#define SOC_IRAM0_CACHE_ADDRESS_HIGH 0x42800000
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/*DRAM0 is connected with Cache DBUS0*/
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#define SOC_DRAM0_ADDRESS_LOW 0x3FC80000
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#define SOC_DRAM0_ADDRESS_HIGH 0x3FCE0000
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#define SOC_DRAM0_CACHE_ADDRESS_LOW 0x3C000000
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#define SOC_DRAM0_CACHE_ADDRESS_HIGH 0x3C800000
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#define SOC_IRAM_FLASH_ADDRESS_LOW SOC_IRAM0_CACHE_ADDRESS_LOW
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#define SOC_IRAM_FLASH_ADDRESS_HIGH SOC_IRAM0_CACHE_ADDRESS_HIGH
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#define SOC_DRAM_FLASH_ADDRESS_LOW SOC_DRAM0_CACHE_ADDRESS_LOW
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#define SOC_DRAM_FLASH_ADDRESS_HIGH SOC_DRAM0_CACHE_ADDRESS_HIGH
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#define SOC_BUS_SIZE(bus_name) (bus_name##_ADDRESS_HIGH - bus_name##_ADDRESS_LOW)
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#define SOC_ADDRESS_IN_BUS(bus_name, vaddr) ((vaddr) >= bus_name##_ADDRESS_LOW && (vaddr) < bus_name##_ADDRESS_HIGH)
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#define SOC_ADDRESS_IN_IRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0, vaddr)
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#define SOC_ADDRESS_IN_IRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_IRAM0_CACHE, vaddr)
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#define SOC_ADDRESS_IN_DRAM0(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0, vaddr)
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#define SOC_ADDRESS_IN_DRAM0_CACHE(vaddr) SOC_ADDRESS_IN_BUS(SOC_DRAM0_CACHE, vaddr)
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#define SOC_MMU_INVALID BIT(8)
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#define SOC_MMU_VALID 0
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#define SOC_MMU_TYPE 0
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#define SOC_MMU_ACCESS_FLASH 0
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/**
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* MMU entry valid bit mask for mapping value. For an entry:
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* valid bit + value bits
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* valid bit is BIT(8), so value bits are 0xff
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*/
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#define SOC_MMU_VALID_VAL_MASK 0xff
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/**
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* Max MMU available paddr page num.
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* `SOC_MMU_MAX_PADDR_PAGE_NUM * SOC_MMU_PAGE_SIZE` means the max paddr address supported by the MMU. e.g.:
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* 256 * 64KB, means MMU can support 16MB paddr at most
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*/
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#define SOC_MMU_MAX_PADDR_PAGE_NUM 256
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/**
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* This is the mask used for mapping. e.g.:
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* 0x4200_0000 & SOC_MMU_VADDR_MASK
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*/
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#define SOC_MMU_VADDR_MASK 0x7FFFFF
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//MMU entry num
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#define SOC_MMU_ENTRY_NUM 128
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#define SOC_MMU_DBUS_VADDR_BASE 0x3C000000
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#define SOC_MMU_IBUS_VADDR_BASE 0x42000000
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/*------------------------------------------------------------------------------
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* MMU Linear Address
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*----------------------------------------------------------------------------*/
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/**
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* - 64KB MMU page size: the last 0xFFFF, which is the offset
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* - 128 MMU entries, needs 0x7F to hold it.
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*
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* Therefore, 0x7F,FFFF
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*/
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#define SOC_MMU_LINEAR_ADDR_MASK 0x7FFFFF
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/**
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* - If high linear address isn't 0, this means MMU can recognize these addresses
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* - If high linear address is 0, this means MMU linear address range is equal or smaller than vaddr range.
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* Under this condition, we use the max linear space.
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*/
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW (SOC_IRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#if ((SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_IRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#else
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#define SOC_MMU_IRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
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#endif
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#define SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW (SOC_DRAM0_CACHE_ADDRESS_LOW & SOC_MMU_LINEAR_ADDR_MASK)
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#if ((SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK) > 0)
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#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_DRAM0_CACHE_ADDRESS_HIGH & SOC_MMU_LINEAR_ADDR_MASK)
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#else
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#define SOC_MMU_DRAM0_LINEAR_ADDRESS_HIGH (SOC_MMU_LINEAR_ADDR_MASK + 1)
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#endif
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/**
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* I/D share the MMU linear address range
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*/
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#ifndef __cplusplus
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_Static_assert(SOC_MMU_IRAM0_LINEAR_ADDRESS_LOW == SOC_MMU_DRAM0_LINEAR_ADDRESS_LOW, "IRAM0 and DRAM0 linear address should be same");
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#endif
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/**
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* ROM flash mmap driver needs below definitions
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*/
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#define BUS_IRAM0_CACHE_SIZE SOC_BUS_SIZE(SOC_IRAM0_CACHE)
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#define BUS_DRAM0_CACHE_SIZE SOC_BUS_SIZE(SOC_DRAM0_CACHE)
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#define CACHE_IBUS 0
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#define CACHE_IBUS_MMU_START 0
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#define CACHE_IBUS_MMU_END 0x200
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#define CACHE_DBUS 1
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#define CACHE_DBUS_MMU_START 0
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#define CACHE_DBUS_MMU_END 0x200
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#define CACHE_IROM_MMU_START 0
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#define CACHE_IROM_MMU_END Cache_Get_IROM_MMU_End()
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#define CACHE_IROM_MMU_SIZE (CACHE_IROM_MMU_END - CACHE_IROM_MMU_START)
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#define CACHE_DROM_MMU_START CACHE_IROM_MMU_END
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#define CACHE_DROM_MMU_END Cache_Get_DROM_MMU_End()
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#define CACHE_DROM_MMU_SIZE (CACHE_DROM_MMU_END - CACHE_DROM_MMU_START)
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#define CACHE_DROM_MMU_MAX_END 0x200
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#define ICACHE_MMU_SIZE 0x200
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#define DCACHE_MMU_SIZE 0x200
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#define MMU_BUS_START(i) 0
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#define MMU_BUS_SIZE(i) 0x200
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#ifdef __cplusplus
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}
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#endif
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