esp-idf

Historia

Mahavir Jain d504ca614c Merge branch 'feature/clock_glitch_enable' into 'master' bootloader: Enable clock glitch detection Closes IDF-2453, IDF-1720, IDFGH-5721, and IDFGH-5327 See merge request espressif/esp-idf!14868		2021-09-07 11:38:18 +00:00
..
esp32	i2s: fix write failure on ESP32 in 32bit slave mode	2021-09-03 17:36:44 +08:00
esp32c3	hmac: Added Downstream JTAG enable mode for esp32c3 and esp32s3	2021-09-06 11:06:50 +05:30
esp32h2	esp32h2: Replicated HMAC JTAG downstream enable mode implementation	2021-09-06 11:06:50 +05:30
esp32s2	driver/i2s: refactor for i2s driver layer	2021-09-02 14:33:36 +08:00
esp32s3	Merge branch 'feature/clock_glitch_enable' into 'master'	2021-09-07 11:38:18 +00:00
include/soc	driver/i2s: refactor for i2s driver layer	2021-09-02 14:33:36 +08:00
CMakeLists.txt	Merge branch 'refactor/move_ldscript_to_soc' into 'master'	2021-07-23 11:54:56 +00:00
README.md	soc: descriptive part occupy whole component	2020-10-28 07:21:29 +08:00
component.mk	soc: move peripheral linker scripts out of target component	2021-07-22 12:55:01 +08:00
linker.lf	soc: move implementations to esp_hw_support	2020-10-28 22:38:50 +08:00
lldesc.c	crypto: initial S3 Beta 3 bringup and testing for SHA/AES/RSA/flash enc	2021-05-18 11:25:41 +08:00
soc_include_legacy_warn.c	Whitespace: Automated whitespace fixes (large commit)	2020-11-11 07:36:35 +00:00

README.md

`soc`

The soc component provides hardware description for targets supported by ESP-IDF.

- `xxx_reg.h`   - defines registers related to the hardware
- `xxx_struct.h` - hardware description in C `struct`
- `xxx_channel.h` - definitions for hardware with multiple channels
- `xxx_caps.h`  - features/capabilities of the hardware
- `xxx_pins.h`  - pin definitions
- `xxx_periph.h/*.c`  - includes all headers related to a peripheral; declaration and definition of IO mapping for that hardware