kopia lustrzana https://github.com/espressif/esp-idf
298 wiersze
10 KiB
C
298 wiersze
10 KiB
C
// Copyright 2015-2019 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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// The LL layer for Timer Group register operations.
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// Note that most of the register operations in this layer are non-atomic operations.
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdlib.h>
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#include <stdbool.h>
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#include "hal/wdt_types.h"
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#include "soc/rtc_cntl_periph.h"
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#include "esp_attr.h"
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//Type check wdt_stage_action_t
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_Static_assert(WDT_STAGE_ACTION_OFF == RTC_WDT_STG_SEL_OFF, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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_Static_assert(WDT_STAGE_ACTION_INT == RTC_WDT_STG_SEL_INT, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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_Static_assert(WDT_STAGE_ACTION_RESET_CPU == RTC_WDT_STG_SEL_RESET_CPU, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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_Static_assert(WDT_STAGE_ACTION_RESET_SYSTEM == RTC_WDT_STG_SEL_RESET_SYSTEM, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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_Static_assert(WDT_STAGE_ACTION_RESET_RTC == RTC_WDT_STG_SEL_RESET_RTC, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_stage_action_t");
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//Type check wdt_reset_sig_length_t
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_Static_assert(WDT_RESET_SIG_LENGTH_100ns == RTC_WDT_RESET_LENGTH_100_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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_Static_assert(WDT_RESET_SIG_LENGTH_200ns == RTC_WDT_RESET_LENGTH_200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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_Static_assert(WDT_RESET_SIG_LENGTH_300ns == RTC_WDT_RESET_LENGTH_300_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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_Static_assert(WDT_RESET_SIG_LENGTH_400ns == RTC_WDT_RESET_LENGTH_400_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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_Static_assert(WDT_RESET_SIG_LENGTH_500ns == RTC_WDT_RESET_LENGTH_500_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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_Static_assert(WDT_RESET_SIG_LENGTH_800ns == RTC_WDT_RESET_LENGTH_800_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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_Static_assert(WDT_RESET_SIG_LENGTH_1_6us == RTC_WDT_RESET_LENGTH_1600_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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_Static_assert(WDT_RESET_SIG_LENGTH_3_2us == RTC_WDT_RESET_LENGTH_3200_NS, "Add mapping to LL watchdog timeout behavior, since it's no longer naturally compatible with wdt_reset_sig_length_t");
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/**
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* @brief Enable the RWDT
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void rwdt_ll_enable(rtc_cntl_dev_t *hw)
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{
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hw->wdt_config0.en = 1;
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}
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/**
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* @brief Disable the RWDT
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*
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* @param hw Start address of the peripheral registers.
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* @note This function does not disable the flashboot mode. Therefore, given that
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* the MWDT is disabled using this function, a timeout can still occur
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* if the flashboot mode is simultaneously enabled.
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*/
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FORCE_INLINE_ATTR void rwdt_ll_disable(rtc_cntl_dev_t *hw)
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{
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hw->wdt_config0.en = 0;
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}
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/**
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* @brief Check if the RWDT is enabled
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*
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* @param hw Start address of the peripheral registers.
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* @return True if RTC WDT is enabled
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*/
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FORCE_INLINE_ATTR bool rwdt_ll_check_if_enabled(rtc_cntl_dev_t *hw)
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{
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return (hw->wdt_config0.en) ? true : false;
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}
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/**
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* @brief Configure a particular stage of the RWDT
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*
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* @param hw Start address of the peripheral registers.
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* @param stage Which stage to configure
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* @param timeout Number of timer ticks for the stage to timeout
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* @param behavior What action to take when the stage times out
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*/
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FORCE_INLINE_ATTR void rwdt_ll_config_stage(rtc_cntl_dev_t *hw, wdt_stage_t stage, uint32_t timeout_ticks, wdt_stage_action_t behavior)
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{
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switch (stage) {
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case WDT_STAGE0:
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hw->wdt_config0.stg0 = behavior;
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hw->wdt_config1 = timeout_ticks;
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break;
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case WDT_STAGE1:
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hw->wdt_config0.stg1 = behavior;
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hw->wdt_config2 = timeout_ticks;
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break;
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case WDT_STAGE2:
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hw->wdt_config0.stg2 = behavior;
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hw->wdt_config3 = timeout_ticks;
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break;
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case WDT_STAGE3:
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hw->wdt_config0.stg3 = behavior;
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hw->wdt_config4 = timeout_ticks;
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break;
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default:
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abort();
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}
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}
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/**
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* @brief Disable a particular stage of the RWDT
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*
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* @param hw Start address of the peripheral registers.
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* @param stage Which stage to disable
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*/
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FORCE_INLINE_ATTR void rwdt_ll_disable_stage(rtc_cntl_dev_t *hw, wdt_stage_t stage)
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{
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switch (stage) {
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case WDT_STAGE0:
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hw->wdt_config0.stg0 = WDT_STAGE_ACTION_OFF;
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break;
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case WDT_STAGE1:
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hw->wdt_config0.stg1 = WDT_STAGE_ACTION_OFF;
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break;
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case WDT_STAGE2:
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hw->wdt_config0.stg2 = WDT_STAGE_ACTION_OFF;
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break;
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case WDT_STAGE3:
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hw->wdt_config0.stg3 = WDT_STAGE_ACTION_OFF;
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break;
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default:
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abort();
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}
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}
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/**
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* @brief Enable or disable RWDT edge interrupt
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*
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* @param hw Start address of the peripheral registers.
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* @param enable Whether to enable edge interrupt
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*/
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FORCE_INLINE_ATTR void rwdt_ll_set_edge_intr(rtc_cntl_dev_t *hw, bool enable)
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{
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hw->wdt_config0.edge_int_en = (enable) ? 1 : 0;
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}
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/**
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* @brief Enable or disable RWDT level interrupt
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*
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* @param hw Start address of the peripheral registers.
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* @param enable Whether to enable level interrupt
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*/
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FORCE_INLINE_ATTR void rwdt_ll_set_level_intr(rtc_cntl_dev_t *hw, bool enable)
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{
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hw->wdt_config0.level_int_en = (enable) ? 1 : 0;
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}
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/**
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* @brief Set the length of the CPU reset action
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*
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* @param hw Start address of the peripheral registers.
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* @param length Length of CPU reset signal
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*/
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FORCE_INLINE_ATTR void rwdt_ll_set_cpu_reset_length(rtc_cntl_dev_t *hw, wdt_reset_sig_length_t length)
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{
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hw->wdt_config0.cpu_reset_length = length;
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}
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/**
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* @brief Set the length of the system reset action
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*
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* @param hw Start address of the peripheral registers.
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* @param length Length of system reset signal
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*/
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FORCE_INLINE_ATTR void rwdt_ll_set_sys_reset_length(rtc_cntl_dev_t *hw, wdt_reset_sig_length_t length)
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{
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hw->wdt_config0.sys_reset_length = length;
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}
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/**
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* @brief Enable/Disable the RWDT flashboot mode.
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*
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* @param hw Start address of the peripheral registers.
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* @param enable True to enable RWDT flashboot mode, false to disable RWDT flashboot mode.
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*
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* @note Flashboot mode is independent and can trigger a WDT timeout event if the
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* WDT's enable bit is set to 0. Flashboot mode for RWDT is automatically enabled
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* on flashboot, and should be disabled by software when flashbooting completes.
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*/
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FORCE_INLINE_ATTR void rwdt_ll_set_flashboot_en(rtc_cntl_dev_t* hw, bool enable)
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{
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hw->wdt_config0.flashboot_mod_en = (enable) ? 1 : 0;
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}
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/**
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* @brief Enable/Disable the CPU0 to be reset on WDT_STAGE_ACTION_RESET_CPU
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*
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* @param hw Start address of the peripheral registers.
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* @param enable True to enable CPU0 to be reset, false to disable.
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*/
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FORCE_INLINE_ATTR void rwdt_ll_set_procpu_reset_en(rtc_cntl_dev_t* hw, bool enable)
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{
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hw->wdt_config0.procpu_reset_en = (enable) ? 1 : 0;
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}
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/**
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* @brief Enable/Disable the CPU1 to be reset on WDT_STAGE_ACTION_RESET_CPU
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*
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* @param hw Start address of the peripheral registers.
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* @param enable True to enable CPU1 to be reset, false to disable.
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*/
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FORCE_INLINE_ATTR void rwdt_ll_set_appcpu_reset_en(rtc_cntl_dev_t* hw, bool enable)
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{
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hw->wdt_config0.appcpu_reset_en = (enable) ? 1 : 0;
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}
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/**
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* @brief Enable/Disable the RWDT pause during sleep functionality
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*
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* @param hw Start address of the peripheral registers.
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* @param enable True to enable, false to disable.
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*/
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FORCE_INLINE_ATTR void rwdt_ll_set_pause_in_sleep_en(rtc_cntl_dev_t* hw, bool enable)
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{
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hw->wdt_config0.pause_in_slp = (enable) ? 1 : 0;
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}
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/**
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* @brief Feed the RWDT
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*
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* Resets the current timer count and current stage.
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void rwdt_ll_feed(rtc_cntl_dev_t *hw)
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{
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hw->wdt_feed.feed = 1;
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}
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/**
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* @brief Enable write protection of the RWDT registers
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void rwdt_ll_write_protect_enable(rtc_cntl_dev_t *hw)
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{
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hw->wdt_wprotect = 0;
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}
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/**
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* @brief Disable write protection of the RWDT registers
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void rwdt_ll_write_protect_disable(rtc_cntl_dev_t *hw)
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{
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hw->wdt_wprotect = RTC_CNTL_WDT_WKEY_VALUE;
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}
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/**
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* @brief Enable the RWDT interrupt.
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*
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* @param hw Start address of the peripheral registers.
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* @param enable True to enable RWDT interrupt, false to disable.
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*/
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FORCE_INLINE_ATTR void rwdt_ll_set_intr_enable(rtc_cntl_dev_t* hw, bool enable)
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{
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hw->int_ena.rtc_wdt = (enable) ? 1 : 0;
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}
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/**
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* @brief Check if the RWDT interrupt has been triggered
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*
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* @param hw Start address of the peripheral registers.
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* @return True if the RWDT interrupt was triggered
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*/
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FORCE_INLINE_ATTR bool rwdt_ll_check_intr_status(rtc_cntl_dev_t *hw)
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{
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return (hw->int_st.rtc_wdt) ? true : false;
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}
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/**
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* @brief Clear the RWDT interrupt status.
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*
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* @param hw Start address of the peripheral registers.
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*/
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FORCE_INLINE_ATTR void rwdt_ll_clear_intr_status(rtc_cntl_dev_t* hw)
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{
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hw->int_clr.rtc_wdt = 1;
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}
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#ifdef __cplusplus
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}
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#endif
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