kopia lustrzana https://github.com/espressif/esp-idf
214 wiersze
6.9 KiB
C
214 wiersze
6.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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//////////////////////////////////////////////////////////
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// ESP32-S3 PMS memory protection types
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//
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#pragma once
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#include <stdint.h>
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#include <stdbool.h>
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#include "soc/soc.h"
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#include "freertos/FreeRTOSConfig.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Memory types recognized by PMS
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*/
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typedef enum {
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MEMPROT_TYPE_NONE = 0x00000000,
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MEMPROT_TYPE_IRAM0_SRAM = 0x00000001,
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MEMPROT_TYPE_DRAM0_SRAM = 0x00000002,
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MEMPROT_TYPE_IRAM0_RTCFAST = 0x00000004,
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MEMPROT_TYPE_ALL = 0x7FFFFFFF,
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MEMPROT_TYPE_INVALID = 0x80000000,
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MEMPROT_TYPE_IRAM0_ANY = MEMPROT_TYPE_IRAM0_SRAM | MEMPROT_TYPE_IRAM0_RTCFAST
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} esp_mprot_mem_t;
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/**
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* @brief Splitting address (line) type
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*/
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typedef enum {
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MEMPROT_SPLIT_ADDR_NONE = 0x00000000,
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MEMPROT_SPLIT_ADDR_IRAM0_DRAM0 = 0x00000001,
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MEMPROT_SPLIT_ADDR_IRAM0_LINE_0 = 0x00000002,
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MEMPROT_SPLIT_ADDR_IRAM0_LINE_1 = 0x00000004,
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MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_0 = 0x00000008,
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MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_1 = 0x00000010,
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MEMPROT_SPLIT_ADDR_ALL = 0x7FFFFFFF,
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MEMPROT_SPLIT_ADDR_INVALID = 0x80000000,
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MEMPROT_SPLIT_ADDR_MAIN = MEMPROT_SPLIT_ADDR_IRAM0_DRAM0
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} esp_mprot_split_addr_t;
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/**
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* @brief PMS area type (memory space between adjacent splitting addresses or above/below the main splt.address)
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*/
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typedef enum {
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MEMPROT_PMS_AREA_NONE = 0x00000000,
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MEMPROT_PMS_AREA_IRAM0_0 = 0x00000001,
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MEMPROT_PMS_AREA_IRAM0_1 = 0x00000002,
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MEMPROT_PMS_AREA_IRAM0_2 = 0x00000004,
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MEMPROT_PMS_AREA_IRAM0_3 = 0x00000008,
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MEMPROT_PMS_AREA_DRAM0_0 = 0x00000010,
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MEMPROT_PMS_AREA_DRAM0_1 = 0x00000020,
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MEMPROT_PMS_AREA_DRAM0_2 = 0x00000040,
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MEMPROT_PMS_AREA_DRAM0_3 = 0x00000080,
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MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO = 0x00000100,
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MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI = 0x00000200,
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MEMPROT_PMS_AREA_ICACHE_0 = 0x00000400,
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MEMPROT_PMS_AREA_ICACHE_1 = 0x00000800,
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MEMPROT_PMS_AREA_ALL = 0x7FFFFFFF,
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MEMPROT_PMS_AREA_INVALID = 0x80000000
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} esp_mprot_pms_area_t;
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/**
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* @brief Memory protection configuration
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*/
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typedef struct {
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bool invoke_panic_handler; /*!< Register PMS violation interrupt for panic-handling */
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bool lock_feature; /*!< Lock all PMS settings */
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void *split_addr; /*!< Main I/D splitting address */
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uint32_t mem_type_mask; /*!< Memory types required to protect. See esp_mprot_mem_t enum */
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size_t target_cpu_count; /*!< Real CPU/core count (max 2) */
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int target_cpu[portNUM_PROCESSORS]; /*!< Array of CPU/core IDs required to receive given PMS protection */
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} esp_memp_config_t;
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//2-CPU configuration
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#if portNUM_PROCESSORS > 1
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//default IDF configuration (basic memory regions, split line detection, locked, panic mode on)
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#define ESP_MEMPROT_DEFAULT_CONFIG() { \
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.invoke_panic_handler = true, \
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.lock_feature = true, \
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.split_addr = NULL, \
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.mem_type_mask = MEMPROT_TYPE_ALL, \
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.target_cpu_count = 2, \
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.target_cpu = {PRO_CPU_NUM, APP_CPU_NUM} \
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}
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//zero (no-go) configuration
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#define ESP_MEMPROT_ZERO_CONFIG() { \
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.target_cpu_count = 2, \
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.target_cpu = {PRO_CPU_NUM, APP_CPU_NUM} \
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}
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#else //1-CPU configuration
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#define ESP_MEMPROT_DEFAULT_CONFIG() { \
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.invoke_panic_handler = true, \
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.lock_feature = true, \
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.split_addr = NULL, \
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.mem_type_mask = MEMPROT_TYPE_ALL, \
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.target_cpu_count = 1, \
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.target_cpu = {PRO_CPU_NUM} \
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}
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#define ESP_MEMPROT_ZERO_CONFIG() { \
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.target_cpu_count = 1, \
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.target_cpu = {PRO_CPU_NUM} \
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}
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#endif //end of CPU-count based defines
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/**
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* @brief Converts Memory protection type to string
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*
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* @param mem_type Memory protection type
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*/
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static inline const char *esp_mprot_mem_type_to_str(const esp_mprot_mem_t mem_type)
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{
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switch (mem_type) {
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case MEMPROT_TYPE_NONE:
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return "NONE";
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case MEMPROT_TYPE_IRAM0_SRAM:
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return "IRAM0_SRAM";
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case MEMPROT_TYPE_DRAM0_SRAM:
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return "DRAM0_SRAM";
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case MEMPROT_TYPE_IRAM0_RTCFAST:
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return "IRAM0_RTCFAST";
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case MEMPROT_TYPE_IRAM0_ANY:
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return "IRAM0_ANY";
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case MEMPROT_TYPE_ALL:
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return "ALL";
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default:
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return "INVALID";
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}
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}
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/**
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* @brief Converts Splitting address type to string
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*
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* @param line_type Split line type
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*/
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static inline const char *esp_mprot_split_addr_to_str(const esp_mprot_split_addr_t line_type)
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{
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switch (line_type) {
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case MEMPROT_SPLIT_ADDR_NONE:
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return "SPLIT_ADDR_NONE";
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case MEMPROT_SPLIT_ADDR_IRAM0_DRAM0:
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return "SPLIT_ADDR_IRAM0_DRAM0";
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case MEMPROT_SPLIT_ADDR_IRAM0_LINE_0:
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return "SPLIT_ADDR_IRAM0_LINE_0";
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case MEMPROT_SPLIT_ADDR_IRAM0_LINE_1:
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return "SPLIT_ADDR_IRAM0_LINE_1";
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case MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_0:
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return "SPLIT_ADDR_DRAM0_DMA_LINE_0";
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case MEMPROT_SPLIT_ADDR_DRAM0_DMA_LINE_1:
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return "SPLIT_ADDR_DRAM0_DMA_LINE_1";
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case MEMPROT_SPLIT_ADDR_ALL:
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return "SPLIT_ADDR_ALL";
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default:
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return "SPLIT_ADDR_INVALID";
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}
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}
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/**
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* @brief Converts PMS Area type to string
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*
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* @param area_type PMS Area type
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*/
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static inline const char *esp_mprot_pms_area_to_str(const esp_mprot_pms_area_t area_type)
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{
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switch (area_type) {
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case MEMPROT_PMS_AREA_NONE:
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return "PMS_AREA_NONE";
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case MEMPROT_PMS_AREA_IRAM0_0:
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return "PMS_AREA_IRAM0_0";
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case MEMPROT_PMS_AREA_IRAM0_1:
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return "PMS_AREA_IRAM0_1";
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case MEMPROT_PMS_AREA_IRAM0_2:
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return "PMS_AREA_IRAM0_2";
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case MEMPROT_PMS_AREA_IRAM0_3:
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return "PMS_AREA_IRAM0_3";
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case MEMPROT_PMS_AREA_DRAM0_0:
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return "PMS_AREA_DRAM0_0";
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case MEMPROT_PMS_AREA_DRAM0_1:
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return "PMS_AREA_DRAM0_1";
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case MEMPROT_PMS_AREA_DRAM0_2:
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return "PMS_AREA_DRAM0_2";
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case MEMPROT_PMS_AREA_DRAM0_3:
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return "PMS_AREA_DRAM0_3";
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case MEMPROT_PMS_AREA_IRAM0_RTCFAST_LO:
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return "PMS_AREA_IRAM0_RTCFAST_LO";
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case MEMPROT_PMS_AREA_IRAM0_RTCFAST_HI:
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return "PMS_AREA_IRAM0_RTCFAST_HI";
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case MEMPROT_PMS_AREA_ICACHE_0:
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return "PMS_AREA_ICACHE_0";
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case MEMPROT_PMS_AREA_ICACHE_1:
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return "PMS_AREA_ICACHE_1";
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case MEMPROT_PMS_AREA_ALL:
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return "PMS_AREA_ALL";
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default:
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return "PMS_AREA_INVALID";
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}
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}
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#ifdef __cplusplus
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}
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#endif
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