esp-idf/components
Wangjialin 924daf7b84 bugfix(i2c): reduce speed of I2C master bus reset routine and release SDA
closes https://github.com/espressif/esp-idf/issues/2494
closes https://github.com/espressif/esp-idf/pull/2493
closes https://github.com/espressif/esp-idf/pull/2496

1. Change bus reset to handle interrupted READ sequences.
2. Slow down I2C to 100khz during reset
3. If a SLAVE device was in a read operation when the bus was interrupted, the SLAVE device is controlling SDA.The only bit during the 9 clock cycles of a byte READ the MASTER(ESP32) is guaranteed control over, is during the ACK bit period.
If the SLAVE is sending a stream of ZERO bytes, it will only release SDA during the ACK bit period. The master(ESP32) cannot generate a STOP unless SDA is HIGH. So, this reset code synchronizes the bit stream with, Either, the ACK bit, Or a 1 bit.
2018-11-30 10:08:28 +08:00
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app_trace
app_update
asio
aws_iot
bootloader
bootloader_support
bt
coap
console
cxx
driver
esp-tls
esp32
esp_adc_cal
esp_event
esp_http_client
esp_http_server
esp_https_ota
esp_https_server
esp_ringbuf
espcoredump
esptool_py
ethernet
expat
fatfs
freemodbus
freertos
heap
idf_test
jsmn
json
libsodium
log
lwip
mbedtls
mdns
micro-ecc
mqtt
newlib
nghttp
nvs_flash
openssl
partition_table
protobuf-c
protocomm
pthread
sdmmc
smartconfig_ack
soc
spi_flash
spiffs
tcp_transport
tcpip_adapter
ulp
unity
vfs
wear_levelling
wifi_provisioning
wpa_supplicant
xtensa-debug-module