kopia lustrzana https://github.com/espressif/esp-idf
133 wiersze
4.7 KiB
C
133 wiersze
4.7 KiB
C
/*
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* SPDX-FileCopyrightText: 2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The LL layer for Cache register operations
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#pragma once
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#include <stdbool.h>
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#include "soc/extmem_reg.h"
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#include "soc/ext_mem_defs.h"
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#include "hal/cache_types.h"
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#include "hal/assert.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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#define CACHE_LL_DEFAULT_IBUS_MASK CACHE_BUS_IBUS0
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#define CACHE_LL_DEFAULT_DBUS_MASK CACHE_BUS_IBUS2
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/**
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* @brief Get the buses of a particular cache that are mapped to a virtual address range
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*
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* External virtual address can only be accessed when the involved cache buses are enabled.
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* This API is to get the cache buses where the memory region (from `vaddr_start` to `vaddr_start + len`) reside.
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param vaddr_start virtual address start
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* @param len vaddr length
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline cache_bus_mask_t cache_ll_l1_get_bus(uint32_t cache_id, uint32_t vaddr_start, uint32_t len)
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{
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HAL_ASSERT(cache_id == 0);
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cache_bus_mask_t mask = 0;
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uint32_t vaddr_end = vaddr_start + len;
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if (vaddr_start >= IRAM1_ADDRESS_LOW) {
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mask |= CACHE_BUS_IBUS1;
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} else if (vaddr_start >= IRAM0_CACHE_ADDRESS_LOW) {
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mask |= CACHE_BUS_IBUS0;
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mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
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} else if (vaddr_start >= DRAM0_CACHE_ADDRESS_LOW) {
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mask |= CACHE_BUS_DBUS0;
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mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
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mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
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} else if (vaddr_start >= DRAM1_ADDRESS_LOW) {
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mask |= CACHE_BUS_DBUS1;
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mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
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mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
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mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
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} else if (vaddr_start >= DPORT_CACHE_ADDRESS_LOW) {
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mask |= CACHE_BUS_DBUS2;
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mask |= (vaddr_end >= DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0;
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mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
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mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
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mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
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} else if (vaddr_start >= DROM0_ADDRESS_LOW) {
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mask |= CACHE_BUS_IBUS2;
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mask |= (vaddr_end >= DPORT_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS2 : 0;
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mask |= (vaddr_end >= DRAM1_ADDRESS_LOW) ? CACHE_BUS_DBUS1 : 0;
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mask |= (vaddr_end >= DRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_DBUS0 : 0;
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mask |= (vaddr_end >= IRAM0_CACHE_ADDRESS_LOW) ? CACHE_BUS_IBUS0 : 0;
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mask |= (vaddr_end >= IRAM1_ADDRESS_LOW) ? CACHE_BUS_IBUS1 : 0;
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} else {
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abort();
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}
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return mask;
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}
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/**
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* Enable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be enabled
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*/
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#if !BOOTLOADER_BUILD
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__attribute__((always_inline))
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#endif
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static inline void cache_ll_l1_enable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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HAL_ASSERT(cache_id == 0);
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uint32_t ibus_mask = 0;
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ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0;
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ibus_mask |= (mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0;
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ibus_mask |= (mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0;
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REG_CLR_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
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uint32_t dbus_mask = 0;
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dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0;
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dbus_mask |= (mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0;
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dbus_mask |= (mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0;
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REG_CLR_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
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}
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/**
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* Disable the Cache Buses
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*
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* @param cache_id cache ID (when l1 cache is per core)
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* @param mask To know which buses should be disabled
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*/
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__attribute__((always_inline))
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static inline void cache_ll_l1_disable_bus(uint32_t cache_id, cache_bus_mask_t mask)
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{
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HAL_ASSERT(cache_id == 0);
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uint32_t ibus_mask = 0;
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ibus_mask |= (mask & CACHE_BUS_IBUS0) ? EXTMEM_PRO_ICACHE_MASK_IRAM0 : 0;
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ibus_mask |= (mask & CACHE_BUS_IBUS1) ? EXTMEM_PRO_ICACHE_MASK_IRAM1 : 0;
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ibus_mask |= (mask & CACHE_BUS_IBUS2) ? EXTMEM_PRO_ICACHE_MASK_DROM0 : 0;
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REG_SET_BIT(EXTMEM_PRO_ICACHE_CTRL1_REG, ibus_mask);
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uint32_t dbus_mask = 0;
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dbus_mask |= (mask & CACHE_BUS_DBUS0) ? EXTMEM_PRO_DCACHE_MASK_DRAM0 : 0;
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dbus_mask |= (mask & CACHE_BUS_DBUS1) ? EXTMEM_PRO_DCACHE_MASK_DRAM1 : 0;
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dbus_mask |= (mask & CACHE_BUS_DBUS2) ? EXTMEM_PRO_DCACHE_MASK_DPORT : 0;
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REG_SET_BIT(EXTMEM_PRO_DCACHE_CTRL1_REG, dbus_mask);
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}
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#ifdef __cplusplus
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}
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#endif
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