kopia lustrzana https://github.com/espressif/esp-idf
398 wiersze
16 KiB
C
398 wiersze
16 KiB
C
// Copyright 2015-2016 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include <string.h>
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#include "driver/spi_master.h"
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#include "soc/gpio_sig_map.h"
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#include "soc/spi_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/spi_struct.h"
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#include "rom/ets_sys.h"
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#include "esp_types.h"
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#include "esp_attr.h"
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#include "esp_intr.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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#include "esp_err.h"
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#include "soc/soc.h"
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#include "soc/dport_reg.h"
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#include "rom/lldesc.h"
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#include "driver/gpio.h"
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#include "driver/periph_ctrl.h"
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#include "esp_heap_caps.h"
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#include "driver/spi_common.h"
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static const char *SPI_TAG = "spi";
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#define SPI_CHECK(a, str, ret_val) \
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if (!(a)) { \
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ESP_LOGE(SPI_TAG,"%s(%d): %s", __FUNCTION__, __LINE__, str); \
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return (ret_val); \
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}
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typedef struct spi_device_t spi_device_t;
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/*
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Stores a bunch of per-spi-peripheral data.
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*/
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typedef struct {
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const uint8_t spiclk_out; //GPIO mux output signals
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const uint8_t spiclk_in;
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const uint8_t spid_out;
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const uint8_t spiq_out;
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const uint8_t spiwp_out;
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const uint8_t spihd_out;
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const uint8_t spid_in; //GPIO mux input signals
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const uint8_t spiq_in;
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const uint8_t spiwp_in;
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const uint8_t spihd_in;
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const uint8_t spics_out[3]; // /CS GPIO output mux signals
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const uint8_t spics_in;
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const uint8_t spiclk_native; //IO pins of IO_MUX muxed signals
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const uint8_t spid_native;
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const uint8_t spiq_native;
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const uint8_t spiwp_native;
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const uint8_t spihd_native;
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const uint8_t spics0_native;
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const uint8_t irq; //irq source for interrupt mux
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const uint8_t irq_dma; //dma irq source for interrupt mux
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const periph_module_t module; //peripheral module, for enabling clock etc
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spi_dev_t *hw; //Pointer to the hardware registers
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} spi_signal_conn_t;
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/*
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Bunch of constants for every SPI peripheral: GPIO signals, irqs, hw addr of registers etc
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*/
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static const spi_signal_conn_t io_signal[3] = {
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{
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.spiclk_out = SPICLK_OUT_IDX,
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.spiclk_in = SPICLK_IN_IDX,
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.spid_out = SPID_OUT_IDX,
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.spiq_out = SPIQ_OUT_IDX,
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.spiwp_out = SPIWP_OUT_IDX,
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.spihd_out = SPIHD_OUT_IDX,
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.spid_in = SPID_IN_IDX,
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.spiq_in = SPIQ_IN_IDX,
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.spiwp_in = SPIWP_IN_IDX,
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.spihd_in = SPIHD_IN_IDX,
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.spics_out = {SPICS0_OUT_IDX, SPICS1_OUT_IDX, SPICS2_OUT_IDX},
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.spics_in = SPICS0_IN_IDX,
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.spiclk_native = 6,
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.spid_native = 8,
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.spiq_native = 7,
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.spiwp_native = 10,
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.spihd_native = 9,
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.spics0_native = 11,
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.irq = ETS_SPI1_INTR_SOURCE,
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.irq_dma = ETS_SPI1_DMA_INTR_SOURCE,
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.module = PERIPH_SPI_MODULE,
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.hw = &SPI1
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}, {
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.spiclk_out = HSPICLK_OUT_IDX,
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.spiclk_in = HSPICLK_IN_IDX,
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.spid_out = HSPID_OUT_IDX,
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.spiq_out = HSPIQ_OUT_IDX,
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.spiwp_out = HSPIWP_OUT_IDX,
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.spihd_out = HSPIHD_OUT_IDX,
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.spid_in = HSPID_IN_IDX,
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.spiq_in = HSPIQ_IN_IDX,
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.spiwp_in = HSPIWP_IN_IDX,
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.spihd_in = HSPIHD_IN_IDX,
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.spics_out = {HSPICS0_OUT_IDX, HSPICS1_OUT_IDX, HSPICS2_OUT_IDX},
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.spics_in = HSPICS0_IN_IDX,
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.spiclk_native = 14,
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.spid_native = 13,
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.spiq_native = 12,
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.spiwp_native = 2,
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.spihd_native = 4,
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.spics0_native = 15,
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.irq = ETS_SPI2_INTR_SOURCE,
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.irq_dma = ETS_SPI2_DMA_INTR_SOURCE,
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.module = PERIPH_HSPI_MODULE,
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.hw = &SPI2
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}, {
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.spiclk_out = VSPICLK_OUT_IDX,
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.spiclk_in = VSPICLK_IN_IDX,
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.spid_out = VSPID_OUT_IDX,
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.spiq_out = VSPIQ_OUT_IDX,
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.spiwp_out = VSPIWP_OUT_IDX,
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.spihd_out = VSPIHD_OUT_IDX,
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.spid_in = VSPID_IN_IDX,
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.spiq_in = VSPIQ_IN_IDX,
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.spiwp_in = VSPIWP_IN_IDX,
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.spihd_in = VSPIHD_IN_IDX,
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.spics_out = {VSPICS0_OUT_IDX, VSPICS1_OUT_IDX, VSPICS2_OUT_IDX},
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.spics_in = VSPICS0_IN_IDX,
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.spiclk_native = 18,
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.spid_native = 23,
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.spiq_native = 19,
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.spiwp_native = 22,
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.spihd_native = 21,
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.spics0_native = 5,
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.irq = ETS_SPI3_INTR_SOURCE,
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.irq_dma = ETS_SPI3_DMA_INTR_SOURCE,
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.module = PERIPH_VSPI_MODULE,
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.hw = &SPI3
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}
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};
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//Periph 1 is 'claimed' by SPI flash code.
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static bool spi_periph_claimed[3] = {true, false, false};
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//Returns true if this peripheral is successfully claimed, false if otherwise.
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bool spicommon_periph_claim(spi_host_device_t host)
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{
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bool ret = __sync_bool_compare_and_swap(&spi_periph_claimed[host], false, true);
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if (ret) periph_module_enable(io_signal[host].module);
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return ret;
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}
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//Returns true if this peripheral is successfully freed, false if otherwise.
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bool spicommon_periph_free(spi_host_device_t host)
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{
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bool ret = __sync_bool_compare_and_swap(&spi_periph_claimed[host], true, false);
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if (ret) periph_module_disable(io_signal[host].module);
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return ret;
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}
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int spicommon_irqsource_for_host(spi_host_device_t host)
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{
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return io_signal[host].irq;
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}
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spi_dev_t *spicommon_hw_for_host(spi_host_device_t host)
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{
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return io_signal[host].hw;
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}
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/*
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Do the common stuff to hook up a SPI host to a bus defined by a bunch of GPIO pins. Feed it a host number and a
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bus config struct and it'll set up the GPIO matrix and enable the device. It will set is_native to 1 if the bus
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config can be done using the IOMUX instead of using the GPIO matrix.
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*/
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esp_err_t spicommon_bus_initialize_io(spi_host_device_t host, const spi_bus_config_t *bus_config, int dma_chan, int flags, bool *is_native)
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{
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bool native = true;
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bool use_quad = (flags & SPICOMMON_BUSFLAG_QUAD) != 0;
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SPI_CHECK(bus_config->mosi_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->mosi_io_num), "spid pin invalid", ESP_ERR_INVALID_ARG);
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SPI_CHECK(bus_config->sclk_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->sclk_io_num), "spiclk pin invalid", ESP_ERR_INVALID_ARG);
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SPI_CHECK(bus_config->miso_io_num < 0 || GPIO_IS_VALID_GPIO(bus_config->miso_io_num), "spiq pin invalid", ESP_ERR_INVALID_ARG);
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if (use_quad) {
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SPI_CHECK(bus_config->quadwp_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->quadwp_io_num), "spiwp pin invalid", ESP_ERR_INVALID_ARG);
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SPI_CHECK(bus_config->quadhd_io_num < 0 || GPIO_IS_VALID_OUTPUT_GPIO(bus_config->quadhd_io_num), "spihd pin invalid", ESP_ERR_INVALID_ARG);
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}
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//Check if the selected pins correspond to the native pins of the peripheral
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if (bus_config->mosi_io_num >= 0 && bus_config->mosi_io_num != io_signal[host].spid_native) native = false;
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if (bus_config->miso_io_num >= 0 && bus_config->miso_io_num != io_signal[host].spiq_native) native = false;
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if (bus_config->sclk_io_num >= 0 && bus_config->sclk_io_num != io_signal[host].spiclk_native) native = false;
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if (use_quad) {
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if (bus_config->quadwp_io_num >= 0 && bus_config->quadwp_io_num != io_signal[host].spiwp_native) native = false;
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if (bus_config->quadhd_io_num >= 0 && bus_config->quadhd_io_num != io_signal[host].spihd_native) native = false;
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}
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*is_native = native;
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if (native) {
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//All SPI native pin selections resolve to 1, so we put that here instead of trying to figure
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//out which FUNC_GPIOx_xSPIxx to grab; they all are defined to 1 anyway.
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if (bus_config->mosi_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], 1);
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if (bus_config->miso_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->miso_io_num], 1);
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if (use_quad && bus_config->quadwp_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], 1);
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if (use_quad && bus_config->quadhd_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], 1);
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if (bus_config->sclk_io_num > 0) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], 1);
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} else {
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//Use GPIO
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if (bus_config->mosi_io_num > 0) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->mosi_io_num], PIN_FUNC_GPIO);
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gpio_set_direction(bus_config->mosi_io_num, GPIO_MODE_INPUT_OUTPUT);
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gpio_matrix_out(bus_config->mosi_io_num, io_signal[host].spid_out, false, false);
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gpio_matrix_in(bus_config->mosi_io_num, io_signal[host].spid_in, false);
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}
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if (bus_config->miso_io_num > 0) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->miso_io_num], PIN_FUNC_GPIO);
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gpio_set_direction(bus_config->miso_io_num, GPIO_MODE_INPUT_OUTPUT);
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gpio_matrix_out(bus_config->miso_io_num, io_signal[host].spiq_out, false, false);
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gpio_matrix_in(bus_config->miso_io_num, io_signal[host].spiq_in, false);
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}
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if (use_quad && bus_config->quadwp_io_num > 0) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadwp_io_num], PIN_FUNC_GPIO);
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gpio_set_direction(bus_config->quadwp_io_num, GPIO_MODE_INPUT_OUTPUT);
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gpio_matrix_out(bus_config->quadwp_io_num, io_signal[host].spiwp_out, false, false);
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gpio_matrix_in(bus_config->quadwp_io_num, io_signal[host].spiwp_in, false);
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}
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if (use_quad && bus_config->quadhd_io_num > 0) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->quadhd_io_num], PIN_FUNC_GPIO);
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gpio_set_direction(bus_config->quadhd_io_num, GPIO_MODE_INPUT_OUTPUT);
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gpio_matrix_out(bus_config->quadhd_io_num, io_signal[host].spihd_out, false, false);
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gpio_matrix_in(bus_config->quadhd_io_num, io_signal[host].spihd_in, false);
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}
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if (bus_config->sclk_io_num > 0) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[bus_config->sclk_io_num], PIN_FUNC_GPIO);
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gpio_set_direction(bus_config->sclk_io_num, GPIO_MODE_INPUT_OUTPUT);
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gpio_matrix_out(bus_config->sclk_io_num, io_signal[host].spiclk_out, false, false);
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gpio_matrix_in(bus_config->sclk_io_num, io_signal[host].spiclk_in, false);
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}
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}
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//Select DMA channel.
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DPORT_SET_PERI_REG_BITS(DPORT_SPI_DMA_CHAN_SEL_REG, 3, dma_chan, (host * 2));
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return ESP_OK;
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}
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//Find any pin with output muxed to ``func`` and reset it to GPIO
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static void reset_func_to_gpio(int func)
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{
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for (int x = 0; x < GPIO_PIN_COUNT; x++) {
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if (GPIO_IS_VALID_GPIO(x) && (READ_PERI_REG(GPIO_FUNC0_OUT_SEL_CFG_REG + (x * 4))&GPIO_FUNC0_OUT_SEL_M) == func) {
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gpio_matrix_out(x, SIG_GPIO_OUT_IDX, false, false);
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}
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}
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}
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esp_err_t spicommon_bus_free_io(spi_host_device_t host)
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{
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if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spid_native], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spid_native], PIN_FUNC_GPIO);
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if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spiq_native], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spiq_native], PIN_FUNC_GPIO);
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if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spiclk_native], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spiclk_native], PIN_FUNC_GPIO);
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if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spiwp_native], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spiwp_native], PIN_FUNC_GPIO);
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if (REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spihd_native], MCU_SEL) == 1) PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spihd_native], PIN_FUNC_GPIO);
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reset_func_to_gpio(io_signal[host].spid_out);
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reset_func_to_gpio(io_signal[host].spiq_out);
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reset_func_to_gpio(io_signal[host].spiclk_out);
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reset_func_to_gpio(io_signal[host].spiwp_out);
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reset_func_to_gpio(io_signal[host].spihd_out);
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return ESP_OK;
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}
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void spicommon_cs_initialize(spi_host_device_t host, int cs_io_num, int cs_num, int force_gpio_matrix)
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{
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if (!force_gpio_matrix && cs_io_num == io_signal[host].spics0_native && cs_num == 0) {
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//The cs0s for all SPI peripherals map to pin mux source 1, so we use that instead of a define.
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cs_io_num], 1);
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} else {
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//Use GPIO matrix
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[cs_io_num], PIN_FUNC_GPIO);
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gpio_matrix_out(cs_io_num, io_signal[host].spics_out[cs_num], false, false);
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if (cs_num == 0) gpio_matrix_in(cs_io_num, io_signal[host].spics_in, false);
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}
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}
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void spicommon_cs_free(spi_host_device_t host, int cs_io_num)
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{
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if (cs_io_num == 0 && REG_GET_FIELD(GPIO_PIN_MUX_REG[io_signal[host].spics0_native], MCU_SEL) == 1) {
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PIN_FUNC_SELECT(GPIO_PIN_MUX_REG[io_signal[host].spics0_native], PIN_FUNC_GPIO);
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}
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reset_func_to_gpio(io_signal[host].spics_out[cs_io_num]);
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}
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//Set up a list of dma descriptors. dmadesc is an array of descriptors. Data is the buffer to point to.
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void spicommon_setup_dma_desc_links(lldesc_t *dmadesc, int len, const uint8_t *data, bool isrx)
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{
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int n = 0;
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while (len) {
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int dmachunklen = len;
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if (dmachunklen > SPI_MAX_DMA_LEN) dmachunklen = SPI_MAX_DMA_LEN;
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if (isrx) {
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//Receive needs DMA length rounded to next 32-bit boundary
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dmadesc[n].size = (dmachunklen + 3) & (~3);
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dmadesc[n].length = (dmachunklen + 3) & (~3);
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} else {
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dmadesc[n].size = dmachunklen;
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dmadesc[n].length = dmachunklen;
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}
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dmadesc[n].buf = (uint8_t *)data;
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dmadesc[n].eof = 0;
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dmadesc[n].sosf = 0;
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dmadesc[n].owner = 1;
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dmadesc[n].qe.stqe_next = &dmadesc[n + 1];
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len -= dmachunklen;
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data += dmachunklen;
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n++;
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}
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dmadesc[n - 1].eof = 1; //Mark last DMA desc as end of stream.
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dmadesc[n - 1].qe.stqe_next = NULL;
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}
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/*
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Code for workaround for DMA issue in ESP32 v0/v1 silicon
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*/
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static volatile int dmaworkaround_channels_busy[2] = {0, 0};
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static dmaworkaround_cb_t dmaworkaround_cb;
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static void *dmaworkaround_cb_arg;
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static portMUX_TYPE dmaworkaround_mux = portMUX_INITIALIZER_UNLOCKED;
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static int dmaworkaround_waiting_for_chan = 0;
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bool IRAM_ATTR spicommon_dmaworkaround_req_reset(int dmachan, dmaworkaround_cb_t cb, void *arg)
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{
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int otherchan = (dmachan == 1) ? 2 : 1;
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bool ret;
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portENTER_CRITICAL(&dmaworkaround_mux);
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if (dmaworkaround_channels_busy[otherchan-1]) {
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//Other channel is busy. Call back when it's done.
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dmaworkaround_cb = cb;
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dmaworkaround_cb_arg = arg;
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dmaworkaround_waiting_for_chan = otherchan;
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ret = false;
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} else {
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//Reset DMA
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DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
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DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
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ret = true;
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}
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portEXIT_CRITICAL(&dmaworkaround_mux);
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return ret;
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}
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|
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bool IRAM_ATTR spicommon_dmaworkaround_reset_in_progress()
|
|
{
|
|
return (dmaworkaround_waiting_for_chan != 0);
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|
}
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|
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void IRAM_ATTR spicommon_dmaworkaround_idle(int dmachan)
|
|
{
|
|
portENTER_CRITICAL(&dmaworkaround_mux);
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|
dmaworkaround_channels_busy[dmachan-1] = 0;
|
|
if (dmaworkaround_waiting_for_chan == dmachan) {
|
|
//Reset DMA
|
|
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
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|
DPORT_CLEAR_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG, DPORT_SPI_DMA_RST);
|
|
dmaworkaround_waiting_for_chan = 0;
|
|
//Call callback
|
|
dmaworkaround_cb(dmaworkaround_cb_arg);
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|
|
|
}
|
|
portEXIT_CRITICAL(&dmaworkaround_mux);
|
|
}
|
|
|
|
void IRAM_ATTR spicommon_dmaworkaround_transfer_active(int dmachan)
|
|
{
|
|
portENTER_CRITICAL(&dmaworkaround_mux);
|
|
dmaworkaround_channels_busy[dmachan-1] = 1;
|
|
portEXIT_CRITICAL(&dmaworkaround_mux);
|
|
}
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|
|
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|