kopia lustrzana https://github.com/espressif/esp-idf
845 wiersze
30 KiB
C
845 wiersze
30 KiB
C
/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: CC0-1.0
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*/
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/**
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* I2S test environment UT_T1_I2S:
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* We use internal signals instead of external wiring, but please keep the following IO connections, or connect nothing to prevent the signal from being disturbed.
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* connect GPIO15 and GPIO19, GPIO25(ESP32)/GPIO17(ESP32-S2) and GPIO26, GPIO21 and GPIO22(ESP32)/GPIO20(ESP32-S2)
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* Please do not connect GPIO32(ESP32) any pull-up resistors externally, it will be used to test i2s adc function.
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*/
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#include <stdio.h>
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#include <string.h>
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#include "freertos/FreeRTOS.h"
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#include "freertos/task.h"
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#include "freertos/queue.h"
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#include "driver/i2s.h"
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#include "hal/i2s_hal.h"
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#include "driver/gpio.h"
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#include "hal/gpio_hal.h"
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#include "unity.h"
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#include "math.h"
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#include "esp_rom_gpio.h"
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#define SAMPLE_RATE (36000)
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#define SAMPLE_BITS (16)
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#if CONFIG_IDF_TARGET_ESP32
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#define MASTER_BCK_IO 15
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#define MASTER_WS_IO 25
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#define SLAVE_BCK_IO 19
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#define SLAVE_WS_IO 26
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#define DATA_IN_IO 21
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#define DATA_OUT_IO 22
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#define ADC1_CHANNEL_4_IO 32
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#define I2S0_DATA_OUT_IDX I2S0O_DATA_OUT23_IDX
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#define I2S0_DATA_IN_IDX I2S0I_DATA_IN15_IDX
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#define I2S1_DATA_OUT_IDX I2S1O_DATA_OUT23_IDX
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#define I2S1_DATA_IN_IDX I2S1I_DATA_IN15_IDX
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#elif CONFIG_IDF_TARGET_ESP32S2
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#define MASTER_BCK_IO 15
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#define MASTER_WS_IO 28
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#define SLAVE_BCK_IO 19
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#define SLAVE_WS_IO 26
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#define DATA_IN_IO 21
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#define DATA_OUT_IO 20
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#define I2S0_DATA_OUT_IDX I2S0O_DATA_OUT23_IDX
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#define I2S0_DATA_IN_IDX I2S0I_DATA_IN15_IDX
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#elif CONFIG_IDF_TARGET_ESP32C3
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// TODO: change pins
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#define MASTER_BCK_IO 4
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#define MASTER_WS_IO 5
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#define SLAVE_BCK_IO 14
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#define SLAVE_WS_IO 15
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#define DATA_IN_IO 19
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#define DATA_OUT_IO 18
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#define I2S0_DATA_OUT_IDX I2SO_SD_OUT_IDX
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#define I2S0_DATA_IN_IDX I2SI_SD_IN_IDX
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#elif CONFIG_IDF_TARGET_ESP32S3
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#define MASTER_BCK_IO 4
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#define MASTER_WS_IO 5
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#define SLAVE_BCK_IO 14
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#define SLAVE_WS_IO 15
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#define DATA_IN_IO 19
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#define DATA_OUT_IO 18
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#define I2S0_DATA_OUT_IDX I2S0O_SD_OUT_IDX
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#define I2S0_DATA_IN_IDX I2S0I_SD_IN_IDX
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#define I2S1_DATA_OUT_IDX I2S1O_SD_OUT_IDX
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#define I2S1_DATA_IN_IDX I2S1I_SD_IN_IDX
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#endif
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#define PERCENT_DIFF 0.0001
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#define I2S_TEST_MODE_SLAVE_TO_MAXTER 0
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#define I2S_TEST_MODE_MASTER_TO_SLAVE 1
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#define I2S_TEST_MODE_LOOPBACK 2
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// mode: 0, master rx, slave tx. mode: 1, master tx, slave rx. mode: 2, master tx rx loopback
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// Since ESP32-S2 has only one I2S, only loop back test can be tested.
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static void i2s_test_io_config(int mode)
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{
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// Connect internal signals using IO matrix.
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[MASTER_BCK_IO], PIN_FUNC_GPIO);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[MASTER_WS_IO], PIN_FUNC_GPIO);
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gpio_hal_iomux_func_sel(GPIO_PIN_MUX_REG[DATA_OUT_IO], PIN_FUNC_GPIO);
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gpio_set_direction(MASTER_BCK_IO, GPIO_MODE_INPUT_OUTPUT);
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gpio_set_direction(MASTER_WS_IO, GPIO_MODE_INPUT_OUTPUT);
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gpio_set_direction(DATA_OUT_IO, GPIO_MODE_INPUT_OUTPUT);
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switch (mode) {
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#if SOC_I2S_NUM > 1
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case I2S_TEST_MODE_SLAVE_TO_MAXTER: {
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esp_rom_gpio_connect_out_signal(MASTER_BCK_IO, I2S0I_BCK_OUT_IDX, 0, 0);
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esp_rom_gpio_connect_in_signal(MASTER_BCK_IO, I2S1O_BCK_IN_IDX, 0);
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esp_rom_gpio_connect_out_signal(MASTER_WS_IO, I2S0I_WS_OUT_IDX, 0, 0);
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esp_rom_gpio_connect_in_signal(MASTER_WS_IO, I2S1O_WS_IN_IDX, 0);
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esp_rom_gpio_connect_out_signal(DATA_OUT_IO, I2S1_DATA_OUT_IDX, 0, 0);
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esp_rom_gpio_connect_in_signal(DATA_OUT_IO, I2S0_DATA_IN_IDX, 0);
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}
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break;
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case I2S_TEST_MODE_MASTER_TO_SLAVE: {
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esp_rom_gpio_connect_out_signal(MASTER_BCK_IO, I2S0O_BCK_OUT_IDX, 0, 0);
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esp_rom_gpio_connect_in_signal(MASTER_BCK_IO, I2S1I_BCK_IN_IDX, 0);
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esp_rom_gpio_connect_out_signal(MASTER_WS_IO, I2S0O_WS_OUT_IDX, 0, 0);
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esp_rom_gpio_connect_in_signal(MASTER_WS_IO, I2S1I_WS_IN_IDX, 0);
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esp_rom_gpio_connect_out_signal(DATA_OUT_IO, I2S0_DATA_OUT_IDX, 0, 0);
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esp_rom_gpio_connect_in_signal(DATA_OUT_IO, I2S1_DATA_IN_IDX, 0);
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}
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break;
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#endif
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case I2S_TEST_MODE_LOOPBACK: {
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esp_rom_gpio_connect_out_signal(DATA_OUT_IO, I2S0_DATA_OUT_IDX, 0, 0);
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esp_rom_gpio_connect_in_signal(DATA_OUT_IO, I2S0_DATA_IN_IDX, 0);
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}
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break;
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default: {
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TEST_FAIL_MESSAGE("error: mode not supported");
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}
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break;
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}
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}
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/**
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* i2s initialize test
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* 1. i2s_driver_install
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* 2. i2s_set_pin
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*/
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TEST_CASE("I2S basic driver install, uninstall, set pin test", "[i2s]")
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{
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// dac, adc i2s
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i2s_config_t i2s_config = {
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.mode = I2S_MODE_MASTER | I2S_MODE_TX,
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.sample_rate = SAMPLE_RATE,
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.bits_per_sample = SAMPLE_BITS,
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.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
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.communication_format = I2S_COMM_FORMAT_STAND_I2S,
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.dma_buf_count = 6,
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.dma_buf_len = 60,
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.use_apll = 0,
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.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
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#if SOC_I2S_SUPPORTS_TDM
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.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
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.total_chan = 2,
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.left_align = false,
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.big_edin = false,
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.bit_order_msb = false,
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.skip_msk = false
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#endif
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};
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// normal i2s
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i2s_pin_config_t pin_config = {
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.mck_io_num = -1,
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.bck_io_num = MASTER_BCK_IO,
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.ws_io_num = MASTER_WS_IO,
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.data_out_num = DATA_OUT_IO,
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.data_in_num = -1
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};
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QueueHandle_t evt_que;
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TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 16, &evt_que));
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TEST_ASSERT(evt_que);
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TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
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TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
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//error param test
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TEST_ASSERT(i2s_driver_install(I2S_NUM_MAX, &i2s_config, 0, NULL) == ESP_ERR_INVALID_ARG);
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TEST_ASSERT(i2s_driver_install(I2S_NUM_0, NULL, 0, NULL) == ESP_ERR_INVALID_ARG);
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i2s_config.dma_buf_count = 1;
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TEST_ASSERT(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL) == ESP_ERR_INVALID_ARG);
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i2s_config.dma_buf_count = 129;
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TEST_ASSERT(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL) == ESP_ERR_INVALID_ARG);
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TEST_ASSERT_EQUAL(ESP_ERR_INVALID_STATE, i2s_driver_uninstall(I2S_NUM_0));
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}
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/**
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* @brief Test mono and stereo mode of I2S by loopback
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* @note Only rx channel distinguish left mono and right mono, tx channel does not
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* @note 1. Check switch mono/stereo by 'i2s_set_clk'
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* 2. Check rx right mono and left mono (requiring tx works in stereo mode)
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* 3. Check tx mono (requiring rx works in stereo mode)
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*/
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TEST_CASE("I2S_mono_stereo_loopback_test", "[i2s]")
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{
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#define WRITE_BUF_LEN 2000
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#define READ_BUF_LEN 4000
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// master driver installed and send data
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i2s_config_t master_i2s_config = {
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.mode = I2S_MODE_MASTER | I2S_MODE_TX | I2S_MODE_RX,
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.sample_rate = SAMPLE_RATE,
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.bits_per_sample = SAMPLE_BITS,
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.channel_format = I2S_CHANNEL_FMT_ONLY_RIGHT,
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.communication_format = I2S_COMM_FORMAT_STAND_MSB,
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.dma_buf_count = 6,
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.dma_buf_len = 100,
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.use_apll = 0,
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.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
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#if SOC_I2S_SUPPORTS_TDM
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.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
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.total_chan = 2,
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.left_align = false,
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.big_edin = false,
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.bit_order_msb = false,
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.skip_msk = false
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#endif
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};
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i2s_pin_config_t master_pin_config = {
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.mck_io_num = -1,
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.bck_io_num = MASTER_BCK_IO,
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.ws_io_num = MASTER_WS_IO,
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.data_out_num = DATA_OUT_IO,
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.data_in_num = DATA_IN_IO
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};
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/* Install I2S in duplex mode */
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TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
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TEST_ESP_OK(i2s_stop(I2S_NUM_0));
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/* Config TX as stereo channel directly, because legacy driver can't support config tx&rx separately */
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#if !SOC_I2S_SUPPORTS_TDM
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i2s_ll_tx_set_chan_mod(&I2S0, 0);
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#else
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i2s_ll_tx_set_active_chan_mask(&I2S0, 0x03);
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#endif
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i2s_ll_tx_enable_mono_mode(&I2S0, false);
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TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
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i2s_test_io_config(I2S_TEST_MODE_LOOPBACK);
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TEST_ESP_OK(i2s_start(I2S_NUM_0));
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uint16_t *w_buf = calloc(1, WRITE_BUF_LEN);
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uint16_t *r_buf = calloc(1, READ_BUF_LEN);
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size_t w_bytes = 0;
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size_t r_bytes = 0;
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for (int n = 0; n < WRITE_BUF_LEN / 2; n++) {
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w_buf[n] = n%100;
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}
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/* rx right mono test
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* tx format: 0x00[L] 0x01[R] 0x02[L] 0x03[R] ...
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* rx receive: 0x01[R] 0x03[R] ... */
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TEST_ESP_OK(i2s_write(I2S_NUM_0, w_buf, WRITE_BUF_LEN, &w_bytes, portMAX_DELAY));
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TEST_ESP_OK(i2s_read(I2S_NUM_0, r_buf, READ_BUF_LEN, &r_bytes, portMAX_DELAY));
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#if CONFIG_IDF_TARGET_ESP32
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/* The data of tx/rx channels are flipped on ESP32 */
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for (int n = 0; n < READ_BUF_LEN / 2; n += 2) {
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int16_t temp = r_buf[n];
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r_buf[n] = r_buf[n+1];
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r_buf[n+1] = temp;
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}
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#endif
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int i = 0;
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for (i = 0; (i < READ_BUF_LEN / 2); i++) {
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if (r_buf[i] == 1) {
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printf("%d %d %d %d\n%d %d %d %d\n",
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r_buf[i], r_buf[i+1], r_buf[i+2], r_buf[i+3],
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r_buf[i+4], r_buf[i+5], r_buf[i+6], r_buf[i+7]);
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break;
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}
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}
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printf("Data start index: %d\n", i);
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TEST_ASSERT(i < READ_BUF_LEN / 2 - 50);
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for (int16_t j = 1; j < 100; j += 2) {
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TEST_ASSERT_EQUAL_INT16(r_buf[i++], j);
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}
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printf("rx right mono test passed\n");
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/* tx/rx stereo test
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* tx format: 0x00[L] 0x01[R] 0x02[L] 0x03[R] ...
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* rx receive: 0x00[L] 0x01[R] 0x02[L] 0x03[R] ... */
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TEST_ESP_OK(i2s_set_clk(I2S_NUM_0, SAMPLE_RATE, SAMPLE_BITS, I2S_CHANNEL_STEREO));
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TEST_ESP_OK(i2s_write(I2S_NUM_0, w_buf, WRITE_BUF_LEN, &w_bytes, portMAX_DELAY));
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TEST_ESP_OK(i2s_read(I2S_NUM_0, r_buf, READ_BUF_LEN, &r_bytes, portMAX_DELAY));
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for (i = 0; (i < READ_BUF_LEN / 2); i++) {
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if (r_buf[i] == 1) {
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printf("%d %d %d %d\n%d %d %d %d\n",
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r_buf[i], r_buf[i+1], r_buf[i+2], r_buf[i+3],
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r_buf[i+4], r_buf[i+5], r_buf[i+6], r_buf[i+7]);
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break;
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}
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}
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printf("Data start index: %d\n", i);
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TEST_ASSERT(i < READ_BUF_LEN / 2 - 100);
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for (int16_t j = 1; j < 100; j ++) {
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TEST_ASSERT_EQUAL_INT16(r_buf[i++], j); // receive all number
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}
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printf("tx/rx stereo test passed\n");
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/* tx mono rx right mono test
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* tx format: 0x01[L] 0x01[R] 0x02[L] 0x02[R] ...
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* rx receive: 0x01[R] 0x02[R] ... */
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TEST_ESP_OK(i2s_set_clk(I2S_NUM_0, SAMPLE_RATE, I2S_BITS_PER_SAMPLE_32BIT, I2S_CHANNEL_MONO));
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TEST_ESP_OK(i2s_write(I2S_NUM_0, w_buf, WRITE_BUF_LEN, &w_bytes, portMAX_DELAY));
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TEST_ESP_OK(i2s_read(I2S_NUM_0, r_buf, READ_BUF_LEN, &r_bytes, portMAX_DELAY));
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for (i = 0; i < READ_BUF_LEN / 2; i++) {
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if (r_buf[i] == 1) {
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printf("%d %d %d %d\n%d %d %d %d\n",
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r_buf[i], r_buf[i+1], r_buf[i+2], r_buf[i+3],
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r_buf[i+4], r_buf[i+5], r_buf[i+6], r_buf[i+7]);
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break;
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}
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}
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printf("Data start index: %d\n", i);
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TEST_ASSERT(i < READ_BUF_LEN / 2 - 100);
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for (int16_t j = 1; j < 100; j ++) {
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TEST_ASSERT_EQUAL_INT16(r_buf[i++], j);
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}
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printf("tx/rx mono test passed\n");
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/* Reinstalling I2S to test rx left mono */
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TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
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master_i2s_config.channel_format = I2S_CHANNEL_FMT_ONLY_LEFT;
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TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
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TEST_ESP_OK(i2s_stop(I2S_NUM_0));
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#if !SOC_I2S_SUPPORTS_TDM
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i2s_ll_tx_set_chan_mod(&I2S0, 0);
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#else
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i2s_ll_tx_set_active_chan_mask(&I2S0, 0x03);
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#endif
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i2s_ll_tx_enable_mono_mode(&I2S0, false);
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i2s_ll_tx_enable_mono_mode(&I2S0, false);
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TEST_ESP_OK(i2s_start(I2S_NUM_0));
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/* rx left mono test
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* tx format: 0x00[L] 0x01[R] 0x02[L] 0x03[R] ...
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* rx receive: 0x00[R] 0x02[R] ... */
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TEST_ESP_OK(i2s_write(I2S_NUM_0, w_buf, WRITE_BUF_LEN, &w_bytes, portMAX_DELAY));
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TEST_ESP_OK(i2s_read(I2S_NUM_0, r_buf, READ_BUF_LEN, &r_bytes, portMAX_DELAY));
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#if CONFIG_IDF_TARGET_ESP32
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/* The data of tx/rx channels are flipped on ESP32 */
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for (int n = 0; n < READ_BUF_LEN / 2; n += 2) {
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int16_t temp = r_buf[n];
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r_buf[n] = r_buf[n+1];
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r_buf[n+1] = temp;
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}
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#endif
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for (i = 0; (i < READ_BUF_LEN / 2); i++) {
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if (r_buf[i] == 2) {
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printf("%d %d %d %d\n%d %d %d %d\n",
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r_buf[i], r_buf[i+1], r_buf[i+2], r_buf[i+3],
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r_buf[i+4], r_buf[i+5], r_buf[i+6], r_buf[i+7]);
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break;
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}
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}
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printf("Data start index: %d\n", i);
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TEST_ASSERT(i < READ_BUF_LEN / 2 - 50);
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for (int16_t j = 2; j < 100; j += 2) {
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TEST_ASSERT_EQUAL_INT16(r_buf[i++], j);
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}
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printf("rx left mono test passed\n");
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free(w_buf);
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free(r_buf);
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TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
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}
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#if SOC_I2S_SUPPORTS_TDM
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TEST_CASE("I2S TDM Loopback test(master tx and rx)", "[i2s]")
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{
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// master driver installed and send data
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i2s_config_t master_i2s_config = {
|
|
.mode = I2S_MODE_MASTER | I2S_MODE_TX | I2S_MODE_RX,
|
|
.sample_rate = SAMPLE_RATE,
|
|
.bits_per_sample = SAMPLE_BITS,
|
|
.channel_format = I2S_CHANNEL_FMT_MULTIPLE,
|
|
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
|
|
.total_chan = 4,
|
|
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1 | I2S_TDM_ACTIVE_CH2 | I2S_TDM_ACTIVE_CH3,
|
|
.dma_buf_count = 6,
|
|
.dma_buf_len = 100,
|
|
.use_apll = 0,
|
|
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
|
|
};
|
|
i2s_pin_config_t master_pin_config = {
|
|
.mck_io_num = -1,
|
|
.bck_io_num = MASTER_BCK_IO,
|
|
.ws_io_num = MASTER_WS_IO,
|
|
.data_out_num = DATA_OUT_IO,
|
|
.data_in_num = DATA_IN_IO
|
|
};
|
|
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
|
|
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
|
|
i2s_test_io_config(I2S_TEST_MODE_LOOPBACK);
|
|
printf("\r\nheap size: %d\n", esp_get_free_heap_size());
|
|
|
|
uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400);
|
|
size_t i2s_bytes_write = 0;
|
|
size_t bytes_read = 0;
|
|
int length = 0;
|
|
uint8_t *i2s_read_buff = (uint8_t *)malloc(sizeof(uint8_t) * 10000);
|
|
|
|
for (int i = 0; i < 100; i++) {
|
|
data_wr[i] = i + 1;
|
|
}
|
|
int flag = 0; // break loop flag
|
|
int end_position = 0;
|
|
// write data to slave
|
|
i2s_write(I2S_NUM_0, data_wr, sizeof(uint8_t) * 400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
|
|
while (!flag) {
|
|
if (length >= 10000 - 500) {
|
|
break;
|
|
}
|
|
i2s_read(I2S_NUM_0, i2s_read_buff + length, sizeof(uint8_t) * 500, &bytes_read, 1000 / portMAX_DELAY);
|
|
if (bytes_read > 0) {
|
|
for (int i = length; i < length + bytes_read; i++) {
|
|
if (i2s_read_buff[i] == 100) {
|
|
flag = 1;
|
|
end_position = i;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
length = length + bytes_read;
|
|
}
|
|
// test the read data right or not
|
|
for (int i = end_position - 99; i <= end_position; i++) {
|
|
TEST_ASSERT_EQUAL_UINT8((i - end_position + 100), *(i2s_read_buff + i));
|
|
}
|
|
free(data_wr);
|
|
free(i2s_read_buff);
|
|
i2s_driver_uninstall(I2S_NUM_0);
|
|
}
|
|
#endif
|
|
|
|
#if SOC_I2S_NUM > 1
|
|
/* ESP32S2 and ESP32C3 has only single I2S port and hence following test cases are not applicable */
|
|
TEST_CASE("I2S write and read test(master tx and slave rx)", "[i2s]")
|
|
{
|
|
// master driver installed and send data
|
|
i2s_config_t master_i2s_config = {
|
|
.mode = I2S_MODE_MASTER | I2S_MODE_TX,
|
|
.sample_rate = SAMPLE_RATE,
|
|
.bits_per_sample = SAMPLE_BITS,
|
|
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
|
|
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
|
|
.dma_buf_count = 6,
|
|
.dma_buf_len = 100,
|
|
.use_apll = 0,
|
|
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
|
|
#if SOC_I2S_SUPPORTS_TDM
|
|
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
|
|
.total_chan = 2,
|
|
.left_align = false,
|
|
.big_edin = false,
|
|
.bit_order_msb = false,
|
|
.skip_msk = false
|
|
#endif
|
|
};
|
|
i2s_pin_config_t master_pin_config = {
|
|
.mck_io_num = -1,
|
|
.bck_io_num = MASTER_BCK_IO,
|
|
.ws_io_num = MASTER_WS_IO,
|
|
.data_out_num = DATA_OUT_IO,
|
|
.data_in_num = -1
|
|
};
|
|
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
|
|
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
|
|
i2s_test_io_config(I2S_TEST_MODE_MASTER_TO_SLAVE);
|
|
printf("\r\nheap size: %d\n", esp_get_free_heap_size());
|
|
|
|
i2s_config_t slave_i2s_config = {
|
|
.mode = I2S_MODE_SLAVE | I2S_MODE_RX,
|
|
.sample_rate = SAMPLE_RATE,
|
|
.bits_per_sample = SAMPLE_BITS,
|
|
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
|
|
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
|
|
.dma_buf_count = 6,
|
|
.dma_buf_len = 100,
|
|
.use_apll = 0,
|
|
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
|
|
#if SOC_I2S_SUPPORTS_TDM
|
|
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
|
|
.total_chan = 2,
|
|
.left_align = false,
|
|
.big_edin = false,
|
|
.bit_order_msb = false,
|
|
.skip_msk = false
|
|
#endif
|
|
};
|
|
i2s_pin_config_t slave_pin_config = {
|
|
.mck_io_num = -1,
|
|
.bck_io_num = SLAVE_BCK_IO,
|
|
.ws_io_num = SLAVE_WS_IO,
|
|
.data_out_num = -1,
|
|
.data_in_num = DATA_IN_IO,
|
|
};
|
|
// slave driver installed and receive data
|
|
TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL));
|
|
TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config));
|
|
i2s_test_io_config(I2S_TEST_MODE_MASTER_TO_SLAVE);
|
|
printf("\r\nheap size: %d\n", esp_get_free_heap_size());
|
|
|
|
uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400);
|
|
size_t i2s_bytes_write = 0;
|
|
size_t bytes_read = 0;
|
|
int length = 0;
|
|
uint8_t *i2s_read_buff = (uint8_t *)malloc(sizeof(uint8_t) * 10000);
|
|
|
|
for (int i = 0; i < 100; i++) {
|
|
data_wr[i] = i + 1;
|
|
}
|
|
int flag = 0; // break loop flag
|
|
int end_position = 0;
|
|
// write data to slave
|
|
i2s_write(I2S_NUM_0, data_wr, sizeof(uint8_t) * 400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
|
|
printf("write data size: %d\n", i2s_bytes_write);
|
|
while (!flag) {
|
|
i2s_read(I2S_NUM_1, i2s_read_buff + length, sizeof(uint8_t) * 500, &bytes_read, 1000 / portTICK_PERIOD_MS);
|
|
if (bytes_read > 0) {
|
|
printf("read data size: %d\n", bytes_read);
|
|
for (int i = length; i < length + bytes_read; i++) {
|
|
if (i2s_read_buff[i] == 100) {
|
|
flag = 1;
|
|
end_position = i;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
length = length + bytes_read;
|
|
}
|
|
// test the readed data right or not
|
|
for (int i = end_position - 99; i <= end_position; i++) {
|
|
TEST_ASSERT_EQUAL_UINT8((i - end_position + 100), *(i2s_read_buff + i));
|
|
}
|
|
free(data_wr);
|
|
free(i2s_read_buff);
|
|
i2s_driver_uninstall(I2S_NUM_0);
|
|
i2s_driver_uninstall(I2S_NUM_1);
|
|
}
|
|
|
|
TEST_CASE("I2S write and read test(master rx and slave tx)", "[i2s]")
|
|
{
|
|
// master driver installed and send data
|
|
i2s_config_t master_i2s_config = {
|
|
.mode = I2S_MODE_MASTER | I2S_MODE_RX,
|
|
.sample_rate = SAMPLE_RATE,
|
|
.bits_per_sample = SAMPLE_BITS,
|
|
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
|
|
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
|
|
.dma_buf_count = 6,
|
|
.dma_buf_len = 100,
|
|
.use_apll = 1,
|
|
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
|
|
#if SOC_I2S_SUPPORTS_TDM
|
|
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
|
|
.total_chan = 2,
|
|
.left_align = false,
|
|
.big_edin = false,
|
|
.bit_order_msb = false,
|
|
.skip_msk = false
|
|
#endif
|
|
};
|
|
i2s_pin_config_t master_pin_config = {
|
|
.mck_io_num = -1,
|
|
.bck_io_num = MASTER_BCK_IO,
|
|
.ws_io_num = MASTER_WS_IO,
|
|
.data_out_num = -1,
|
|
.data_in_num = DATA_IN_IO,
|
|
};
|
|
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
|
|
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
|
|
i2s_test_io_config(I2S_TEST_MODE_SLAVE_TO_MAXTER);
|
|
printf("\r\nheap size: %d\n", esp_get_free_heap_size());
|
|
|
|
i2s_config_t slave_i2s_config = {
|
|
.mode = I2S_MODE_SLAVE | I2S_MODE_TX, // Only RX
|
|
.sample_rate = SAMPLE_RATE,
|
|
.bits_per_sample = SAMPLE_BITS,
|
|
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT, //2-channels
|
|
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
|
|
.dma_buf_count = 6,
|
|
.dma_buf_len = 100,
|
|
.use_apll = 1,
|
|
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
|
|
#if SOC_I2S_SUPPORTS_TDM
|
|
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
|
|
.total_chan = 2,
|
|
.left_align = false,
|
|
.big_edin = false,
|
|
.bit_order_msb = false,
|
|
.skip_msk = false
|
|
#endif
|
|
};
|
|
i2s_pin_config_t slave_pin_config = {
|
|
.mck_io_num = -1,
|
|
.bck_io_num = SLAVE_BCK_IO,
|
|
.ws_io_num = SLAVE_WS_IO,
|
|
.data_out_num = DATA_OUT_IO,
|
|
.data_in_num = -1
|
|
};
|
|
// slave driver installed and receive data
|
|
TEST_ESP_OK(i2s_driver_install(I2S_NUM_1, &slave_i2s_config, 0, NULL));
|
|
TEST_ESP_OK(i2s_set_pin(I2S_NUM_1, &slave_pin_config));
|
|
i2s_test_io_config(I2S_TEST_MODE_SLAVE_TO_MAXTER);
|
|
printf("\r\nheap size: %d\n", esp_get_free_heap_size());
|
|
|
|
uint8_t *data_wr = (uint8_t *)malloc(sizeof(uint8_t) * 400);
|
|
size_t i2s_bytes_write = 0;
|
|
size_t bytes_read = 0;
|
|
int length = 0;
|
|
uint8_t *i2s_read_buff = (uint8_t *)malloc(sizeof(uint8_t) * 10000);
|
|
|
|
for (int i = 0; i < 100; i++) {
|
|
data_wr[i] = i + 1;
|
|
}
|
|
// slave write data to master
|
|
i2s_write(I2S_NUM_1, data_wr, sizeof(uint8_t) * 400, &i2s_bytes_write, 1000 / portTICK_PERIOD_MS);
|
|
printf("write data size: %d\n", i2s_bytes_write);
|
|
int flag = 0; // break loop flag
|
|
volatile int end_position = 0;
|
|
// write data to slave
|
|
while (!flag) {
|
|
TEST_ESP_OK(i2s_read(I2S_NUM_0, i2s_read_buff + length, 10000 - length, &bytes_read, 1000 / portTICK_PERIOD_MS));
|
|
if (bytes_read > 0) {
|
|
printf("read data size: %d\n", bytes_read);
|
|
for (int i = length; i < length + bytes_read; i++) {
|
|
if (i2s_read_buff[i] == 100) {
|
|
flag = 1;
|
|
end_position = i;
|
|
break;
|
|
}
|
|
}
|
|
}
|
|
length = length + bytes_read;
|
|
}
|
|
// test the readed data right or not
|
|
for (int i = end_position - 99; i <= end_position; i++) {
|
|
TEST_ASSERT_EQUAL_UINT8((i - end_position + 100), *(i2s_read_buff + i));
|
|
}
|
|
free(data_wr);
|
|
free(i2s_read_buff);
|
|
i2s_driver_uninstall(I2S_NUM_0);
|
|
i2s_driver_uninstall(I2S_NUM_1);
|
|
}
|
|
#endif
|
|
|
|
TEST_CASE("I2S memory leaking test", "[i2s]")
|
|
{
|
|
i2s_config_t master_i2s_config = {
|
|
.mode = I2S_MODE_MASTER | I2S_MODE_RX,
|
|
.sample_rate = SAMPLE_RATE,
|
|
.bits_per_sample = SAMPLE_BITS,
|
|
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
|
|
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
|
|
.dma_buf_count = 6,
|
|
.dma_buf_len = 100,
|
|
.use_apll = 0,
|
|
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
|
|
#if SOC_I2S_SUPPORTS_TDM
|
|
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
|
|
.total_chan = 2,
|
|
.left_align = false,
|
|
.big_edin = false,
|
|
.bit_order_msb = false,
|
|
.skip_msk = false
|
|
#endif
|
|
};
|
|
i2s_pin_config_t master_pin_config = {
|
|
.mck_io_num = -1,
|
|
.bck_io_num = MASTER_BCK_IO,
|
|
.ws_io_num = MASTER_WS_IO,
|
|
.data_out_num = -1,
|
|
.data_in_num = DATA_IN_IO
|
|
};
|
|
|
|
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
|
|
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
|
|
i2s_driver_uninstall(I2S_NUM_0);
|
|
int initial_size = esp_get_free_heap_size();
|
|
|
|
for (int i = 0; i < 100; i++) {
|
|
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &master_i2s_config, 0, NULL));
|
|
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &master_pin_config));
|
|
i2s_driver_uninstall(I2S_NUM_0);
|
|
TEST_ASSERT(initial_size == esp_get_free_heap_size());
|
|
}
|
|
vTaskDelay(100 / portTICK_PERIOD_MS);
|
|
TEST_ASSERT(initial_size == esp_get_free_heap_size());
|
|
}
|
|
|
|
#if SOC_I2S_SUPPORTS_APLL
|
|
/*
|
|
* The I2S APLL clock variation test used to test the difference between the different sample rates, different bits per sample
|
|
* and the APLL clock generate for it. The TEST_CASE passes PERCENT_DIFF variation from the provided sample rate in APLL generated clock
|
|
* The percentage difference calculated as (mod((obtained clock rate - desired clock rate)/(desired clock rate))) * 100.
|
|
*/
|
|
TEST_CASE("I2S APLL clock variation test", "[i2s]")
|
|
{
|
|
i2s_pin_config_t pin_config = {
|
|
.mck_io_num = -1,
|
|
.bck_io_num = MASTER_BCK_IO,
|
|
.ws_io_num = MASTER_WS_IO,
|
|
.data_out_num = DATA_OUT_IO,
|
|
.data_in_num = -1
|
|
};
|
|
|
|
i2s_config_t i2s_config = {
|
|
.mode = I2S_MODE_MASTER | I2S_MODE_TX,
|
|
.sample_rate = SAMPLE_RATE,
|
|
.bits_per_sample = SAMPLE_BITS,
|
|
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
|
|
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
|
|
.dma_buf_count = 6,
|
|
.dma_buf_len = 60,
|
|
.use_apll = true,
|
|
.intr_alloc_flags = 0,
|
|
#if SOC_I2S_SUPPORTS_TDM
|
|
.chan_mask = I2S_TDM_ACTIVE_CH0 | I2S_TDM_ACTIVE_CH1,
|
|
.total_chan = 2,
|
|
.left_align = false,
|
|
.big_edin = false,
|
|
.bit_order_msb = false,
|
|
.skip_msk = false
|
|
#endif
|
|
};
|
|
|
|
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
|
|
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
|
|
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
|
|
int initial_size = esp_get_free_heap_size();
|
|
|
|
uint32_t sample_rate_arr[8] = { 10675, 11025, 16000, 22050, 32000, 44100, 48000, 96000 };
|
|
int bits_per_sample_arr[3] = { 16, 24, 32 };
|
|
|
|
for (int i = 0; i < (sizeof(sample_rate_arr) / sizeof(sample_rate_arr[0])); i++) {
|
|
for (int j = 0; j < (sizeof(bits_per_sample_arr) / sizeof(bits_per_sample_arr[0])); j++) {
|
|
i2s_config.sample_rate = sample_rate_arr[i];
|
|
i2s_config.bits_per_sample = bits_per_sample_arr[j];
|
|
|
|
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
|
|
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, &pin_config));
|
|
TEST_ASSERT((fabs((i2s_get_clk(I2S_NUM_0) - sample_rate_arr[i])) / (sample_rate_arr[i])) * 100 < PERCENT_DIFF);
|
|
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
|
|
TEST_ASSERT(initial_size == esp_get_free_heap_size());
|
|
}
|
|
}
|
|
|
|
vTaskDelay(100 / portTICK_PERIOD_MS);
|
|
TEST_ASSERT(initial_size == esp_get_free_heap_size());
|
|
}
|
|
#endif
|
|
|
|
#if SOC_I2S_SUPPORTS_ADC
|
|
/* Only ESP32 need I2S adc/dac test */
|
|
TEST_CASE("I2S adc test", "[i2s]")
|
|
{
|
|
// init I2S ADC
|
|
i2s_config_t i2s_config = {
|
|
.mode = I2S_MODE_MASTER | I2S_MODE_RX | I2S_MODE_ADC_BUILT_IN,
|
|
.sample_rate = SAMPLE_RATE,
|
|
.bits_per_sample = SAMPLE_BITS,
|
|
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
|
|
.intr_alloc_flags = 0,
|
|
.dma_buf_count = 2,
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.dma_buf_len = 1024,
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|
.use_apll = 0,
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|
};
|
|
// install and start I2S driver
|
|
i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL);
|
|
// init ADC pad
|
|
i2s_set_adc_mode(ADC_UNIT_1, ADC1_CHANNEL_4);
|
|
// enable adc sampling, ADC_WIDTH_BIT_12, ADC_ATTEN_DB_12 hard-coded in adc_i2s_mode_init
|
|
i2s_adc_enable(I2S_NUM_0);
|
|
// init read buffer
|
|
uint16_t *i2sReadBuffer = (uint16_t *)calloc(1024, sizeof(uint16_t));
|
|
size_t bytesRead;
|
|
|
|
for (int loop = 0; loop < 10; loop++) {
|
|
for (int level = 0; level <= 1; level++) {
|
|
if (level == 0) {
|
|
gpio_set_pull_mode(ADC1_CHANNEL_4_IO, GPIO_PULLDOWN_ONLY);
|
|
} else {
|
|
gpio_set_pull_mode(ADC1_CHANNEL_4_IO, GPIO_PULLUP_ONLY);
|
|
}
|
|
vTaskDelay(200 / portTICK_RATE_MS);
|
|
// read data from adc, will block until buffer is full
|
|
i2s_read(I2S_NUM_0, (void *)i2sReadBuffer, 1024 * sizeof(uint16_t), &bytesRead, portMAX_DELAY);
|
|
|
|
// calc average
|
|
int64_t adcSumValue = 0;
|
|
for (size_t i = 0; i < 1024; i++) {
|
|
adcSumValue += i2sReadBuffer[i] & 0xfff;
|
|
}
|
|
int adcAvgValue = adcSumValue / 1024;
|
|
printf("adc average val: %d\n", adcAvgValue);
|
|
|
|
if (level == 0) {
|
|
if (adcAvgValue > 100) {
|
|
i2s_adc_disable(I2S_NUM_0);
|
|
free(i2sReadBuffer);
|
|
i2s_driver_uninstall(I2S_NUM_0);
|
|
TEST_ASSERT_LESS_THAN(100, adcAvgValue);
|
|
}
|
|
} else {
|
|
if (adcAvgValue < 4000) {
|
|
i2s_adc_disable(I2S_NUM_0);
|
|
free(i2sReadBuffer);
|
|
i2s_driver_uninstall(I2S_NUM_0);
|
|
TEST_ASSERT_GREATER_THAN(4000, adcAvgValue);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
i2s_adc_disable(I2S_NUM_0);
|
|
free(i2sReadBuffer);
|
|
i2s_driver_uninstall(I2S_NUM_0);
|
|
}
|
|
#endif
|
|
|
|
#if SOC_I2S_SUPPORTS_DAC
|
|
TEST_CASE("I2S dac test", "[i2s]")
|
|
{
|
|
// dac, adc i2s
|
|
i2s_config_t i2s_config = {
|
|
.mode = I2S_MODE_MASTER | I2S_MODE_TX,
|
|
.sample_rate = SAMPLE_RATE,
|
|
.bits_per_sample = SAMPLE_BITS,
|
|
.channel_format = I2S_CHANNEL_FMT_RIGHT_LEFT,
|
|
.communication_format = I2S_COMM_FORMAT_STAND_I2S,
|
|
.dma_buf_count = 6,
|
|
.dma_buf_len = 60,
|
|
.use_apll = 0,
|
|
.intr_alloc_flags = ESP_INTR_FLAG_LEVEL1,
|
|
};
|
|
|
|
//install and start i2s driver
|
|
TEST_ESP_OK(i2s_driver_install(I2S_NUM_0, &i2s_config, 0, NULL));
|
|
//for internal DAC, this will enable both of the internal channels
|
|
TEST_ESP_OK(i2s_set_pin(I2S_NUM_0, NULL));
|
|
//stop & destroy i2s driver
|
|
TEST_ESP_OK(i2s_driver_uninstall(I2S_NUM_0));
|
|
}
|
|
#endif
|