kopia lustrzana https://github.com/espressif/esp-idf
![]() This commit fixes an issue where in the ULP RISC-V I2C example causes a spurious wakeup of the main CPU because of a Trap signal when the ULP core does not meet the wakeup threshold values. This was due to the fact that the RTC_CNTL_COCPU_DONE signal was being set before the RTC_CNTL_COCPU_SHUT_RESET_EN signal which was causing the the ULP RISC-V core to not reset properly on each cycle. Closes https://github.com/espressif/esp-idf/issues/10301 |
||
---|---|---|
.. | ||
include/ulp_riscv | ||
start.S | ||
ulp_riscv_adc.c | ||
ulp_riscv_utils.c |