kopia lustrzana https://github.com/espressif/esp-idf
286 wiersze
12 KiB
C
286 wiersze
12 KiB
C
/*
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* SPDX-FileCopyrightText: 2010-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdio.h>
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#include <string.h>
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#include <freertos/FreeRTOS.h>
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#include <freertos/task.h>
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#include <freertos/semphr.h>
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#include "unity.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp_sleep.h"
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#include "ulp.h"
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/sens_reg.h"
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#include "soc/rtc_io_reg.h"
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#include "hal/misc.h"
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#include "driver/rtc_io.h"
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#include "sdkconfig.h"
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#include "esp_rom_sys.h"
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#include "ulp_test_app.h"
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/* Test cases that require manual interaction, not run in CI */
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void ulp_fsm_controls_rtc_io(void)
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{
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assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
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/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
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hal_memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
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/* ULP co-processor program to toggle LED */
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const ulp_insn_t program[] = {
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I_MOVI(R0, 0), // r0 is LED state
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I_MOVI(R2, 16), // loop r2 from 16 down to 0
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M_LABEL(4), // define label 4
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I_SUBI(R2, R2, 1), // r2 = r2 - 1
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M_BXZ(6), // branch to label 6 if r2 = 0
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I_ADDI(R0, R0, 1), // r0 = (r0 + 1) % 2
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I_ANDI(R0, R0, 0x1),
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M_BL(0, 1), // if r0 < 1 goto 0
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M_LABEL(1), // define label 1
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I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 1), // RTC_GPIO12 = 1
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M_BX(2), // goto 2
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M_LABEL(0), // define label 0
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I_WR_REG(RTC_GPIO_OUT_REG, 26, 27, 0), // RTC_GPIO12 = 0
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M_LABEL(2), // define label 2
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I_MOVI(R1, 100), // loop R1 from 100 down to 0
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M_LABEL(3), // define label 3
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I_SUBI(R1, R1, 1), // r1 = r1 - 1
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M_BXZ(5), // branch to label 5 if r1 = 0
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I_DELAY(32000), // delay for a while
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M_BX(3), // goto 3
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M_LABEL(5), // define label 5
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M_BX(4), // loop back to label 4
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M_LABEL(6), // define label 6
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I_WAKE(), // wake up the SoC
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I_END(), // stop ULP program timer
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I_HALT()
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};
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/* Configure LED GPIOs */
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const gpio_num_t led_gpios[] = {
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GPIO_NUM_2,
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GPIO_NUM_0,
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GPIO_NUM_4
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};
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for (size_t i = 0; i < sizeof(led_gpios)/sizeof(led_gpios[0]); ++i) {
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rtc_gpio_init(led_gpios[i]);
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rtc_gpio_set_direction(led_gpios[i], RTC_GPIO_MODE_OUTPUT_ONLY);
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rtc_gpio_set_level(led_gpios[i], 0);
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}
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/* Calculate the size of the ULP co-processor binary, load it and run the ULP coprocessor */
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size_t size = sizeof(program)/sizeof(ulp_insn_t);
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TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
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TEST_ESP_OK(ulp_run(0));
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/* Setup wakeup triggers */
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TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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/* Enter Deep Sleep */
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esp_deep_sleep_start();
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UNITY_TEST_FAIL(__LINE__, "Should not get here!");
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}
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void ulp_fsm_power_consumption(void)
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{
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assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 4 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
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/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
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hal_memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
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/* Put the ULP coprocessor in halt state */
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ulp_insn_t insn = I_HALT();
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hal_memcpy(RTC_SLOW_MEM, &insn, sizeof(insn));
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/* Set ULP timer */
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ulp_set_wakeup_period(0, 0x8000);
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/* Run the ULP coprocessor */
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TEST_ESP_OK(ulp_run(0));
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/* Setup wakeup triggers */
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TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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TEST_ASSERT(esp_sleep_enable_timer_wakeup(10 * 1000000) == ESP_OK);
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/* Enter Deep Sleep */
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esp_deep_sleep_start();
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UNITY_TEST_FAIL(__LINE__, "Should not get here!");
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}
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#if !DISABLED_FOR_TARGETS(ESP32)
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void ulp_fsm_temp_sens(void)
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{
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assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
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/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
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hal_memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
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// Allow TSENS to be controlled by the ULP
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SET_PERI_REG_BITS(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_CLK_DIV, 10, SENS_TSENS_CLK_DIV_S);
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#if CONFIG_IDF_TARGET_ESP32S2
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SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, SENS_FORCE_XPD_SAR_FSM, SENS_FORCE_XPD_SAR_S);
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SET_PERI_REG_MASK(SENS_SAR_TSENS_CTRL2_REG, SENS_TSENS_CLKGATE_EN);
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#elif CONFIG_IDF_TARGET_ESP32S3
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SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
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SET_PERI_REG_MASK(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_TSENS_CLK_EN);
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#endif
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CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP);
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CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_DUMP_OUT);
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CLEAR_PERI_REG_MASK(SENS_SAR_TSENS_CTRL_REG, SENS_TSENS_POWER_UP_FORCE);
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// data start offset
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size_t offset = 20;
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// number of samples to collect
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RTC_SLOW_MEM[offset] = (CONFIG_ULP_COPROC_RESERVE_MEM) / 4 - offset - 8;
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// sample counter
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RTC_SLOW_MEM[offset + 1] = 0;
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/* ULP co-processor program to record temperature sensor readings */
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const ulp_insn_t program[] = {
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I_MOVI(R1, offset), // r1 <- offset
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I_LD(R2, R1, 1), // r2 <- counter
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I_LD(R3, R1, 0), // r3 <- length
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I_SUBI(R3, R3, 1), // end = length - 1
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I_SUBR(R3, R3, R2), // r3 = length - counter
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M_BXF(1), // if overflow goto 1:
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I_TSENS(R0, 16383), // r0 <- tsens
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I_ST(R0, R2, offset + 4), // mem[r2 + offset +4] <- r0
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I_ADDI(R2, R2, 1), // counter += 1
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I_ST(R2, R1, 1), // save counter
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I_HALT(), // enter sleep
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M_LABEL(1), // done with measurements
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I_END(), // stop ULP timer
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I_WAKE(), // initiate wakeup
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I_HALT()
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};
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size_t size = sizeof(program)/sizeof(ulp_insn_t);
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TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
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assert(offset >= size);
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/* Run the ULP coprocessor */
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TEST_ESP_OK(ulp_run(0));
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/* Setup wakeup triggers */
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TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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TEST_ASSERT(esp_sleep_enable_timer_wakeup(10 * 1000000) == ESP_OK);
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/* Enter Deep Sleep */
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esp_deep_sleep_start();
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UNITY_TEST_FAIL(__LINE__, "Should not get here!");
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}
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#endif //#if !DISABLED_FOR_TARGETS(ESP32)
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void ulp_fsm_adc(void)
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{
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assert(CONFIG_ULP_COPROC_RESERVE_MEM >= 260 && "this test needs ULP_COPROC_RESERVE_MEM option set in menuconfig");
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const int adc = 0;
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const int channel = 0;
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const int atten = 0;
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/* Clear the RTC_SLOW_MEM region for the ULP co-processor binary to be loaded */
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hal_memset(RTC_SLOW_MEM, 0, CONFIG_ULP_COPROC_RESERVE_MEM);
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#if defined(CONFIG_IDF_TARGET_ESP32)
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// Configure SAR ADCn resolution
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SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR1_BIT_WIDTH, 3, SENS_SAR1_BIT_WIDTH_S);
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SET_PERI_REG_BITS(SENS_SAR_START_FORCE_REG, SENS_SAR2_BIT_WIDTH, 3, SENS_SAR2_BIT_WIDTH_S);
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SET_PERI_REG_BITS(SENS_SAR_READ_CTRL_REG, SENS_SAR1_SAMPLE_BIT, 0x3, SENS_SAR1_SAMPLE_BIT_S);
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SET_PERI_REG_BITS(SENS_SAR_READ_CTRL2_REG, SENS_SAR2_SAMPLE_BIT, 0x3, SENS_SAR2_SAMPLE_BIT_S);
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// SAR ADCn is started by ULP FSM
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START2_REG, SENS_MEAS2_START_FORCE);
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START1_REG, SENS_MEAS1_START_FORCE);
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// Use ULP FSM to power up SAR ADCn
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SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
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SET_PERI_REG_BITS(SENS_SAR_MEAS_WAIT2_REG, SENS_FORCE_XPD_AMP, 2, SENS_FORCE_XPD_AMP_S);
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// SAR ADCn invert result
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SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR1_DATA_INV);
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SET_PERI_REG_MASK(SENS_SAR_READ_CTRL_REG, SENS_SAR2_DATA_INV);
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// Set SAR ADCn pad enable bitmap to be controlled by ULP FSM
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START1_REG, SENS_SAR1_EN_PAD_FORCE_M);
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS_START2_REG, SENS_SAR2_EN_PAD_FORCE_M);
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#elif defined(CONFIG_IDF_TARGET_ESP32S2) || defined(CONFIG_IDF_TARGET_ESP32S3)
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// SAR ADCn is started by ULP FSM
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL2_REG, SENS_MEAS2_START_FORCE);
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_CTRL2_REG, SENS_MEAS1_START_FORCE);
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// Use ULP FSM to power up/down SAR ADCn
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SET_PERI_REG_BITS(SENS_SAR_POWER_XPD_SAR_REG, SENS_FORCE_XPD_SAR, 0, SENS_FORCE_XPD_SAR_S);
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SET_PERI_REG_BITS(SENS_SAR_MEAS1_CTRL1_REG, SENS_FORCE_XPD_AMP, 2, SENS_FORCE_XPD_AMP_S);
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// SAR1 invert result
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SET_PERI_REG_MASK(SENS_SAR_READER1_CTRL_REG, SENS_SAR1_DATA_INV);
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SET_PERI_REG_MASK(SENS_SAR_READER2_CTRL_REG, SENS_SAR2_DATA_INV);
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// Set SAR ADCn pad enable bitmap to be controlled by ULP FSM
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS1_CTRL2_REG, SENS_SAR1_EN_PAD_FORCE_M);
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CLEAR_PERI_REG_MASK(SENS_SAR_MEAS2_CTRL2_REG, SENS_SAR2_EN_PAD_FORCE_M);
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// Enable SAR ADCn clock gate on esp32s3
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#if CONFIG_IDF_TARGET_ESP32S3
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SET_PERI_REG_MASK(SENS_SAR_PERI_CLK_GATE_CONF_REG, SENS_SARADC_CLK_EN);
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#endif
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#endif
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SET_PERI_REG_BITS(SENS_SAR_ATTEN1_REG, 3, atten, 2 * channel); //set SAR1 attenuation
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SET_PERI_REG_BITS(SENS_SAR_ATTEN2_REG, 3, atten, 2 * channel); //set SAR2 attenuation
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// data start offset
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size_t offset = 20;
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// number of samples to collect
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RTC_SLOW_MEM[offset] = (CONFIG_ULP_COPROC_RESERVE_MEM) / 4 - offset - 8;
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// sample counter
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RTC_SLOW_MEM[offset + 1] = 0;
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const ulp_insn_t program[] = {
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I_MOVI(R1, offset), // r1 <- offset
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I_LD(R2, R1, 1), // r2 <- counter
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I_LD(R3, R1, 0), // r3 <- length
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I_SUBI(R3, R3, 1), // end = length - 1
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I_SUBR(R3, R3, R2), // r3 = length - counter
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M_BXF(1), // if overflow goto 1:
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I_ADC(R0, adc, channel), // r0 <- ADC
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I_ST(R0, R2, offset + 4), // mem[r2 + offset +4] = r0
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I_ADDI(R2, R2, 1), // counter += 1
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I_ST(R2, R1, 1), // save counter
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I_HALT(), // enter sleep
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M_LABEL(1), // done with measurements
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I_END(), // stop ULP program timer
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I_HALT()
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};
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size_t size = sizeof(program)/sizeof(ulp_insn_t);
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TEST_ESP_OK(ulp_process_macros_and_load(0, program, &size));
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assert(offset >= size);
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/* Run the ULP coprocessor */
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TEST_ESP_OK(ulp_run(0));
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/* Setup wakeup triggers */
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TEST_ASSERT(esp_sleep_enable_ulp_wakeup() == ESP_OK);
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TEST_ASSERT(esp_sleep_enable_timer_wakeup(10 * 1000000) == ESP_OK);
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/* Enter Deep Sleep */
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esp_deep_sleep_start();
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UNITY_TEST_FAIL(__LINE__, "Should not get here!");
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}
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