kopia lustrzana https://github.com/espressif/esp-idf
293 wiersze
13 KiB
C
293 wiersze
13 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/dport_reg.h"
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#include "soc/gpio_reg.h"
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#include "soc/spi_mem_reg.h"
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#include "soc/extmem_reg.h"
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#include "soc/regi2c_ulp.h"
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#include "hal/efuse_hal.h"
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#include "hal/efuse_ll.h"
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#include "regi2c_ctrl.h"
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#include "esp_hw_log.h"
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#ifndef BOOTLOADER_BUILD
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#include "esp_private/sar_periph_ctrl.h"
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#endif
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__attribute__((unused)) static const char *TAG = "rtc_init";
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static void set_ocode_by_efuse(int calib_version);
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static void calibrate_ocode(void);
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void rtc_init(rtc_config_t cfg)
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{
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/**
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* When run rtc_init, it maybe deep sleep reset. Since we power down modem in deep sleep, after wakeup
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* from deep sleep, these fields are changed and not reset. We will access two BB regs(BBPD_CTRL and
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* NRXPD_CTRL) in rtc_sleep_pu. If PD modem and no iso, CPU will stuck when access these two BB regs
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* and finally triggle RTC WDT. So need to clear modem Force PD.
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*
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* No worry about the power consumption, Because modem Force PD will be set at the end of this function.
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*/
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PVTMON_PU);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, cfg.pll_wait);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, cfg.ck8m_wait);
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/* Moved from rtc sleep to rtc init to save sleep function running time */
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// set shortest possible sleep time limit
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REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_MIN_SLP_VAL, RTC_CNTL_MIN_SLP_VAL_MIN);
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/* This power domian removed
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* set rom&ram timer
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* REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_POWERUP_TIMER, ROM_RAM_POWERUP_CYCLES);
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* REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_ROM_RAM_WAIT_TIMER, ROM_RAM_WAIT_CYCLES);
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*/
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// set wifi timer
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rtc_init_config_t rtc_init_cfg = RTC_INIT_CONFIG_DEFAULT();
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REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_POWERUP_TIMER, rtc_init_cfg.wifi_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER3_REG, RTC_CNTL_WIFI_WAIT_TIMER, rtc_init_cfg.wifi_wait_cycles);
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// set rtc peri timer
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_POWERUP_TIMER, rtc_init_cfg.rtc_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_WAIT_TIMER, rtc_init_cfg.rtc_wait_cycles);
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// set digital wrap timer
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_POWERUP_TIMER, rtc_init_cfg.dg_wrap_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER4_REG, RTC_CNTL_DG_WRAP_WAIT_TIMER, rtc_init_cfg.dg_wrap_wait_cycles);
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// set rtc memory timer
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REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_POWERUP_TIMER, rtc_init_cfg.rtc_mem_powerup_cycles);
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REG_SET_FIELD(RTC_CNTL_TIMER5_REG, RTC_CNTL_RTCMEM_WAIT_TIMER, rtc_init_cfg.rtc_mem_wait_cycles);
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SET_PERI_REG_MASK(RTC_CNTL_BIAS_CONF_REG,
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RTC_CNTL_DEC_HEARTBEAT_WIDTH | RTC_CNTL_INC_HEARTBEAT_PERIOD);
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/* Reset RTC bias to default value (needed if waking up from deep sleep) */
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_WAK, RTC_CNTL_DBIAS_1V10);
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_DBIAS_SLP, RTC_CNTL_DBIAS_1V10);
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/* Set the wait time to the default value. */
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REG_SET_FIELD(RTC_CNTL_TIMER2_REG, RTC_CNTL_ULPCP_TOUCH_START_WAIT, RTC_CNTL_ULPCP_TOUCH_START_WAIT_DEFAULT);
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if (cfg.clkctl_init) {
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//clear CMMU clock force on
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CLEAR_PERI_REG_MASK(EXTMEM_PRO_CACHE_MMU_POWER_CTRL_REG, EXTMEM_PRO_CACHE_MMU_MEM_FORCE_ON);
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//clear rom clock force on
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REG_SET_FIELD(DPORT_ROM_CTRL_0_REG, DPORT_ROM_FO, 0);
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//clear sram clock force on
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REG_SET_FIELD(DPORT_SRAM_CTRL_0_REG, DPORT_SRAM_FO, 0);
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//clear tag clock force on
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CLEAR_PERI_REG_MASK(EXTMEM_PRO_DCACHE_TAG_POWER_CTRL_REG, EXTMEM_PRO_DCACHE_TAG_MEM_FORCE_ON);
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CLEAR_PERI_REG_MASK(EXTMEM_PRO_ICACHE_TAG_POWER_CTRL_REG, EXTMEM_PRO_ICACHE_TAG_MEM_FORCE_ON);
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//clear register clock force on
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CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(0), SPI_MEM_CLK_EN);
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CLEAR_PERI_REG_MASK(SPI_MEM_CLOCK_GATE_REG(1), SPI_MEM_CLK_EN);
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}
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if (cfg.pwrctl_init) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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//cancel xtal force pu if no need to force power up
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//cannot cancel xtal force pu if pll is force power on
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if (!(cfg.xtal_fpu | cfg.bbpll_fpu)) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
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} else {
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_XTL_FORCE_PU);
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}
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// CLEAR APLL close
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_PLLA_FORCE_PD);
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//cancel bbpll force pu if setting no force power up
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if (!cfg.bbpll_fpu) {
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
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} else {
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BBPLL_I2C_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
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}
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//cancel RTC REG force PU
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_REGULATOR_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PU);
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//combine two rtc memory options
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_NOISO);
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if (cfg.rtc_dboost_fpd) {
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SET_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_REG, RTC_CNTL_DBOOST_FORCE_PD);
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}
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//cancel sar i2c pd force
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,RTC_CNTL_SAR_I2C_FORCE_PD);
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//cancel digital pu force
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_MEM_FORCE_PU);
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/* If this mask is enabled, all soc memories cannot enter power down mode */
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/* We should control soc memory power down mode from RTC, so we will not touch this register any more */
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CLEAR_PERI_REG_MASK(DPORT_MEM_PD_MASK_REG, DPORT_LSLP_MEM_PD_MASK);
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/* If this pd_cfg is set to 1, all memory won't enter low power mode during light sleep */
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/* If this pd_cfg is set to 0, all memory will enter low power mode during light sleep */
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rtc_sleep_pd_config_t pd_cfg = RTC_SLEEP_PD_CONFIG_ALL(0);
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rtc_sleep_pd(pd_cfg);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PU);
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// ROM_RAM power domain is removed
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// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_WRAP_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_NOISO);
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// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_CPU_ROM_RAM_FORCE_NOISO);
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CLEAR_PERI_REG_MASK(RTC_CNTL_PWC_REG, RTC_CNTL_FORCE_NOISO);
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//cancel digital PADS force no iso
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if (cfg.cpu_waiti_clk_gate) {
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CLEAR_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_CPU_WAIT_MODE_FORCE_ON);
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} else {
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SET_PERI_REG_MASK(DPORT_CPU_PER_CONF_REG, DPORT_CPU_WAIT_MODE_FORCE_ON);
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}
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/*if DPORT_CPU_WAIT_MODE_FORCE_ON == 0 , the cpu clk will be closed when cpu enter WAITI mode*/
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_UNHOLD);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_DG_PAD_FORCE_NOISO);
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}
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/* force power down wifi and bt power domain */
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SET_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
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#if !CONFIG_IDF_ENV_FPGA
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if (cfg.cali_ocode) {
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uint32_t rtc_calib_version = efuse_ll_get_blk_version_minor(); // IDF-5366
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if (rtc_calib_version == 2) {
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set_ocode_by_efuse(rtc_calib_version);
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} else {
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calibrate_ocode();
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}
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}
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#endif // !CONFIG_IDF_ENV_FPGA
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REG_WRITE(RTC_CNTL_INT_ENA_REG, 0);
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REG_WRITE(RTC_CNTL_INT_CLR_REG, UINT32_MAX);
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#ifndef BOOTLOADER_BUILD
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//initialise SAR related peripheral register settings
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sar_periph_ctrl_init();
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#endif
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}
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rtc_vddsdio_config_t rtc_vddsdio_get_config(void)
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{
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rtc_vddsdio_config_t result;
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uint32_t sdio_conf_reg = REG_READ(RTC_CNTL_SDIO_CONF_REG);
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result.drefh = (sdio_conf_reg & RTC_CNTL_DREFH_SDIO_M) >> RTC_CNTL_DREFH_SDIO_S;
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result.drefm = (sdio_conf_reg & RTC_CNTL_DREFM_SDIO_M) >> RTC_CNTL_DREFM_SDIO_S;
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result.drefl = (sdio_conf_reg & RTC_CNTL_DREFL_SDIO_M) >> RTC_CNTL_DREFL_SDIO_S;
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if (sdio_conf_reg & RTC_CNTL_SDIO_FORCE) {
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// Get configuration from RTC
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result.force = 1;
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result.enable = (sdio_conf_reg & RTC_CNTL_XPD_SDIO_REG_M) >> RTC_CNTL_XPD_SDIO_REG_S;
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result.tieh = (sdio_conf_reg & RTC_CNTL_SDIO_TIEH_M) >> RTC_CNTL_SDIO_TIEH_S;
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return result;
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} else {
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result.force = 0;
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}
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#if 0 // ToDo: re-enable the commented codes
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if (efuse_ll_get_sdio_force()) {
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result.enable = efuse_ll_get_sdio_xpd();
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result.tieh = efuse_ll_get_sdio_tieh();
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result.drefm = efuse_ll_get_sdio_drefm();
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result.drefl = efuse_ll_get_sdio_drefl();
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result.drefh = efuse_ll_get_sdio_drefh();
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return result;
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}
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#endif
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// Otherwise, VDD_SDIO is controlled by bootstrapping pin
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uint32_t strap_reg = REG_READ(GPIO_STRAP_REG);
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result.tieh = (strap_reg & BIT(5)) ? RTC_VDDSDIO_TIEH_1_8V : RTC_VDDSDIO_TIEH_3_3V;
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result.enable = 1;
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return result;
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}
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void rtc_vddsdio_set_config(rtc_vddsdio_config_t config)
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{
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uint32_t val = 0;
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val |= (config.force << RTC_CNTL_SDIO_FORCE_S);
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val |= (config.enable << RTC_CNTL_XPD_SDIO_REG_S);
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val |= (config.drefh << RTC_CNTL_DREFH_SDIO_S);
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val |= (config.drefm << RTC_CNTL_DREFM_SDIO_S);
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val |= (config.drefl << RTC_CNTL_DREFL_SDIO_S);
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val |= (config.tieh << RTC_CNTL_SDIO_TIEH_S);
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val |= RTC_CNTL_SDIO_PD_EN;
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REG_WRITE(RTC_CNTL_SDIO_CONF_REG, val);
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}
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static void set_ocode_by_efuse(int calib_version)
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{
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assert(calib_version == 2);
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uint32_t ocode = efuse_ll_get_ocode();
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if (ocode >> 6) {
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ocode = 93 - (ocode ^ (1 << 6));
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} else {
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ocode = 93 + ocode;
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}
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_EXT_CODE, ocode);
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_CODE, 1);
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}
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/**
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* TODO IDF-4141, this seems influence flash,
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*/
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static void calibrate_ocode(void)
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{
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/*
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Bandgap output voltage is not precise when calibrate o-code by hardware sometimes, so need software o-code calibration (must turn off PLL).
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Method:
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1. read current cpu config, save in old_config;
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2. switch cpu to xtal because PLL will be closed when o-code calibration;
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3. begin o-code calibration;
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4. wait o-code calibration done flag(odone_flag & bg_odone_flag) or timeout;
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5. set cpu to old-config.
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*/
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soc_rtc_slow_clk_src_t slow_clk_src = rtc_clk_slow_src_get();
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rtc_cal_sel_t cal_clk = RTC_CAL_RTC_MUX;
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if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_XTAL32K) {
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cal_clk = RTC_CAL_32K_XTAL;
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} else if (slow_clk_src == SOC_RTC_SLOW_CLK_SRC_RC_FAST_D256) {
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cal_clk = RTC_CAL_8MD256;
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}
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uint64_t max_delay_time_us = 10000;
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uint32_t slow_clk_period = rtc_clk_cal(cal_clk, 100);
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uint64_t max_delay_cycle = rtc_time_us_to_slowclk(max_delay_time_us, slow_clk_period);
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uint64_t cycle0 = rtc_time_get();
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uint64_t timeout_cycle = cycle0 + max_delay_cycle;
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uint64_t cycle1 = 0;
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rtc_cpu_freq_config_t old_config;
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rtc_clk_cpu_freq_get_config(&old_config);
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rtc_clk_cpu_freq_set_xtal();
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 0);
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_RESETB, 1);
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bool odone_flag = 0;
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bool bg_odone_flag = 0;
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while(1) {
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odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_O_DONE_FLAG);
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bg_odone_flag = REGI2C_READ_MASK(I2C_ULP, I2C_ULP_BG_O_DONE_FLAG);
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cycle1 = rtc_time_get();
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if (odone_flag && bg_odone_flag)
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break;
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if (cycle1 >= timeout_cycle) {
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ESP_HW_LOGW(TAG, "o_code calibration fail");
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break;
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}
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}
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rtc_clk_cpu_freq_set_config(&old_config);
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}
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