kopia lustrzana https://github.com/espressif/esp-idf
392 wiersze
11 KiB
C
392 wiersze
11 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <stddef.h>
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#include <assert.h>
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#include <stdlib.h>
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#include "sdkconfig.h"
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#include "esp32p4/rom/ets_sys.h"
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#include "esp32p4/rom/rtc.h"
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#include "soc/rtc.h"
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#include "esp_private/rtc_clk.h"
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#include "esp_hw_log.h"
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#include "esp_rom_sys.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/regi2c_ctrl_ll.h"
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#include "soc/io_mux_reg.h"
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#include "soc/lp_clkrst_reg.h"
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static const char *TAG = "rtc_clk";
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// Current PLL frequency, in 480MHz. Zero if PLL is not enabled.
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static int s_cur_pll_freq;
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static uint32_t s_bbpll_digi_consumers_ref_count = 0; // Currently, it only tracks whether the 48MHz PHY clock is in-use by USB Serial/JTAG
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void rtc_clk_bbpll_add_consumer(void)
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{
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s_bbpll_digi_consumers_ref_count += 1;
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}
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void rtc_clk_bbpll_remove_consumer(void)
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{
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s_bbpll_digi_consumers_ref_count -= 1;
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}
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void rtc_clk_32k_enable(bool enable)
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{
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if (enable) {
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clk_ll_xtal32k_enable(CLK_LL_XTAL32K_ENABLE_MODE_CRYSTAL);
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} else {
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clk_ll_xtal32k_disable();
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}
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}
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void rtc_clk_32k_enable_external(void)
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{
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}
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void rtc_clk_32k_bootstrap(uint32_t cycle)
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{
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/* No special bootstrapping needed for ESP32-P4, 'cycle' argument is to keep the signature
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* same as for the ESP32. Just enable the XTAL here.
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*/
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(void)cycle;
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rtc_clk_32k_enable(true);
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}
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bool rtc_clk_32k_enabled(void)
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{
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return clk_ll_xtal32k_is_enabled();
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}
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void rtc_clk_rc32k_enable(bool enable)
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{
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if (enable) {
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clk_ll_rc32k_enable();
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esp_rom_delay_us(SOC_DELAY_RC32K_ENABLE);
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} else {
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clk_ll_rc32k_disable();
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}
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}
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void rtc_clk_8m_enable(bool clk_8m_en)
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{
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if (clk_8m_en) {
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clk_ll_rc_fast_enable();
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esp_rom_delay_us(SOC_DELAY_RC_FAST_ENABLE);
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} else {
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clk_ll_rc_fast_disable();
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}
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}
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bool rtc_clk_8m_enabled(void)
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{
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return clk_ll_rc_fast_is_enabled();
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}
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void rtc_clk_slow_src_set(soc_rtc_slow_clk_src_t clk_src)
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{
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clk_ll_rtc_slow_set_src(clk_src);
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esp_rom_delay_us(SOC_DELAY_RTC_SLOW_CLK_SWITCH);
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}
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soc_rtc_slow_clk_src_t rtc_clk_slow_src_get(void)
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{
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return clk_ll_rtc_slow_get_src();
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}
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uint32_t rtc_clk_slow_freq_get_hz(void)
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{
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switch (rtc_clk_slow_src_get()) {
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case SOC_RTC_SLOW_CLK_SRC_RC_SLOW: return SOC_CLK_RC_SLOW_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_XTAL32K: return SOC_CLK_XTAL32K_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_RC32K: return SOC_CLK_RC32K_FREQ_APPROX;
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case SOC_RTC_SLOW_CLK_SRC_OSC_SLOW: return SOC_CLK_OSC_SLOW_FREQ_APPROX;
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default: return 0;
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}
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}
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void rtc_clk_fast_src_set(soc_rtc_fast_clk_src_t clk_src)
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{
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clk_ll_rtc_fast_set_src(clk_src);
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esp_rom_delay_us(SOC_DELAY_RTC_FAST_CLK_SWITCH);
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}
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soc_rtc_fast_clk_src_t rtc_clk_fast_src_get(void)
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{
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return clk_ll_rtc_fast_get_src();
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}
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static void rtc_clk_bbpll_disable(void)
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{
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clk_ll_bbpll_disable();
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s_cur_pll_freq = 0;
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}
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static void rtc_clk_bbpll_enable(void)
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{
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clk_ll_bbpll_enable();
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}
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static void rtc_clk_bbpll_configure(rtc_xtal_freq_t xtal_freq, int pll_freq)
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{
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/* Digital part */
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clk_ll_bbpll_set_freq_mhz(pll_freq);
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/* Analog part */
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/* BBPLL CALIBRATION START */
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regi2c_ctrl_ll_bbpll_calibration_start();
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clk_ll_bbpll_set_config(pll_freq, xtal_freq);
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/* WAIT CALIBRATION DONE */
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while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
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/* BBPLL CALIBRATION STOP */
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regi2c_ctrl_ll_bbpll_calibration_stop();
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s_cur_pll_freq = pll_freq;
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}
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/**
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* Switch to use XTAL as the CPU clock source.
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* Must satisfy: cpu_freq = XTAL_FREQ / div.
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* Does not disable the PLL.
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*/
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static void rtc_clk_cpu_freq_to_xtal(int cpu_freq, int div)
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{
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clk_ll_ahb_set_ls_divider(div);
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clk_ll_cpu_set_ls_divider(div);
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_XTAL);
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ets_update_cpu_frequency(cpu_freq);
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}
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static void rtc_clk_cpu_freq_to_8m(void)
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{
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clk_ll_ahb_set_ls_divider(1);
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clk_ll_cpu_set_ls_divider(1);
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_RC_FAST);
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ets_update_cpu_frequency(20);
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}
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/**
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* Switch to one of PLL-based frequencies. Current frequency can be XTAL or PLL.
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* PLL must already be enabled.
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* @param cpu_freq new CPU frequency
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*/
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static void rtc_clk_cpu_freq_to_pll_mhz(int cpu_freq_mhz)
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{
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clk_ll_cpu_set_hs_divider(CLK_LL_PLL_480M_FREQ_MHZ / cpu_freq_mhz);
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clk_ll_cpu_set_src(SOC_CPU_CLK_SRC_PLL);
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ets_update_cpu_frequency(cpu_freq_mhz);
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}
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bool rtc_clk_cpu_freq_mhz_to_config(uint32_t freq_mhz, rtc_cpu_freq_config_t *out_config)
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{
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uint32_t source_freq_mhz;
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soc_cpu_clk_src_t source;
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uint32_t divider; // divider = freq of SOC_ROOT_CLK / freq of CPU_CLK
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uint32_t real_freq_mhz;
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uint32_t xtal_freq = (uint32_t)rtc_clk_xtal_freq_get();
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if (freq_mhz <= xtal_freq && freq_mhz != 0) {
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divider = xtal_freq / freq_mhz;
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real_freq_mhz = (xtal_freq + divider / 2) / divider; /* round */
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if (real_freq_mhz != freq_mhz) {
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// no suitable divider
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return false;
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}
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source_freq_mhz = xtal_freq;
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source = SOC_CPU_CLK_SRC_XTAL;
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} else if (freq_mhz == 80) {
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real_freq_mhz = freq_mhz;
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source = SOC_CPU_CLK_SRC_PLL;
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source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
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divider = 6;
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} else if (freq_mhz == 120) {
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real_freq_mhz = freq_mhz;
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source = SOC_CPU_CLK_SRC_PLL;
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source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
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divider = 4;
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} else if (freq_mhz == 160) {
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real_freq_mhz = freq_mhz;
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source = SOC_CPU_CLK_SRC_PLL;
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source_freq_mhz = CLK_LL_PLL_480M_FREQ_MHZ;
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divider = 3;
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} else {
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// unsupported frequency
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return false;
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}
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*out_config = (rtc_cpu_freq_config_t) {
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.source = source,
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.div = divider,
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.source_freq_mhz = source_freq_mhz,
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.freq_mhz = real_freq_mhz
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};
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return true;
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}
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void rtc_clk_cpu_freq_set_config(const rtc_cpu_freq_config_t *config)
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{
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soc_cpu_clk_src_t old_cpu_clk_src = clk_ll_cpu_get_src();
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if (config->source == SOC_CPU_CLK_SRC_XTAL) {
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rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
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if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
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// We don't turn off the bbpll if some consumers depend on bbpll
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rtc_clk_bbpll_disable();
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}
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} else if (config->source == SOC_CPU_CLK_SRC_PLL) {
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if (old_cpu_clk_src != SOC_CPU_CLK_SRC_PLL) {
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rtc_clk_bbpll_enable();
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rtc_clk_bbpll_configure(rtc_clk_xtal_freq_get(), config->source_freq_mhz);
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}
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rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
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} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
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rtc_clk_cpu_freq_to_8m();
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if ((old_cpu_clk_src == SOC_CPU_CLK_SRC_PLL) && !s_bbpll_digi_consumers_ref_count) {
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// We don't turn off the bbpll if some consumers depend on bbpll
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rtc_clk_bbpll_disable();
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}
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}
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}
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void rtc_clk_cpu_freq_get_config(rtc_cpu_freq_config_t *out_config)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t source_freq_mhz;
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uint32_t div; // div = freq of SOC_ROOT_CLK / freq of CPU_CLK
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uint32_t freq_mhz;
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switch (source) {
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case SOC_CPU_CLK_SRC_XTAL: {
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div = clk_ll_cpu_get_ls_divider();
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source_freq_mhz = (uint32_t)rtc_clk_xtal_freq_get();
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freq_mhz = source_freq_mhz / div;
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break;
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}
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case SOC_CPU_CLK_SRC_PLL: {
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div = clk_ll_cpu_get_hs_divider();
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source_freq_mhz = clk_ll_bbpll_get_freq_mhz();
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freq_mhz = source_freq_mhz / div;
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break;
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}
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case SOC_CPU_CLK_SRC_RC_FAST:
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div = clk_ll_cpu_get_ls_divider();
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source_freq_mhz = 20;
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freq_mhz = source_freq_mhz / div;
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break;
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default:
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ESP_HW_LOGE(TAG, "unsupported frequency configuration");
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abort();
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}
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*out_config = (rtc_cpu_freq_config_t) {
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.source = source,
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.source_freq_mhz = source_freq_mhz,
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.div = div,
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.freq_mhz = freq_mhz
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};
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}
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void rtc_clk_cpu_freq_set_config_fast(const rtc_cpu_freq_config_t *config)
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{
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if (config->source == SOC_CPU_CLK_SRC_XTAL) {
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rtc_clk_cpu_freq_to_xtal(config->freq_mhz, config->div);
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} else if (config->source == SOC_CPU_CLK_SRC_PLL &&
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s_cur_pll_freq == config->source_freq_mhz) {
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rtc_clk_cpu_freq_to_pll_mhz(config->freq_mhz);
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} else if (config->source == SOC_CPU_CLK_SRC_RC_FAST) {
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rtc_clk_cpu_freq_to_8m();
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} else {
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/* fallback */
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rtc_clk_cpu_freq_set_config(config);
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}
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}
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void rtc_clk_cpu_freq_set_xtal(void)
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{
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rtc_clk_cpu_set_to_default_config();
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// We don't turn off the bbpll if some consumers depend on bbpll
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if (!s_bbpll_digi_consumers_ref_count) {
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rtc_clk_bbpll_disable();
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}
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}
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void rtc_clk_cpu_set_to_default_config(void)
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{
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int freq_mhz = (int)rtc_clk_xtal_freq_get();
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rtc_clk_cpu_freq_to_xtal(freq_mhz, 1);
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}
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rtc_xtal_freq_t rtc_clk_xtal_freq_get(void)
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{
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uint32_t xtal_freq_mhz = clk_ll_xtal_load_freq_mhz();
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if (xtal_freq_mhz == 0) {
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ESP_HW_LOGW(TAG, "invalid RTC_XTAL_FREQ_REG value, assume 40MHz");
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return RTC_XTAL_FREQ_40M;
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}
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return (rtc_xtal_freq_t)xtal_freq_mhz;
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}
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void rtc_clk_xtal_freq_update(rtc_xtal_freq_t xtal_freq)
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{
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clk_ll_xtal_store_freq_mhz(xtal_freq);
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}
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static uint32_t rtc_clk_ahb_freq_get(void)
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{
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soc_cpu_clk_src_t source = clk_ll_cpu_get_src();
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uint32_t soc_root_freq_mhz;
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uint32_t divider;
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switch (source) {
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case SOC_CPU_CLK_SRC_XTAL:
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soc_root_freq_mhz = rtc_clk_xtal_freq_get();
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divider = clk_ll_ahb_get_ls_divider();
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break;
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case SOC_CPU_CLK_SRC_PLL:
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soc_root_freq_mhz = clk_ll_bbpll_get_freq_mhz();
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divider = clk_ll_ahb_get_hs_divider();
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break;
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case SOC_CPU_CLK_SRC_RC_FAST:
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soc_root_freq_mhz = 20;
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divider = clk_ll_ahb_get_ls_divider();
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break;
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default:
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// Unknown SOC_ROOT clock source
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soc_root_freq_mhz = 0;
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divider = 1;
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ESP_HW_LOGE(TAG, "Invalid SOC_ROOT_CLK");
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break;
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}
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return soc_root_freq_mhz / divider;
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}
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uint32_t rtc_clk_apb_freq_get(void)
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{
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return rtc_clk_ahb_freq_get() / clk_ll_apb_get_divider() * MHZ;
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}
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void rtc_dig_clk8m_enable(void)
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{
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clk_ll_rc_fast_digi_enable();
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esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH);
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}
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void rtc_dig_clk8m_disable(void)
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{
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clk_ll_rc_fast_digi_disable();
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esp_rom_delay_us(SOC_DELAY_RC_FAST_DIGI_SWITCH);
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}
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bool rtc_dig_8m_enabled(void)
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{
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return clk_ll_rc_fast_digi_is_enabled();
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}
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/* Name used in libphy.a:phy_chip_v7.o
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* TODO: update the library to use rtc_clk_xtal_freq_get
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*/
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rtc_xtal_freq_t rtc_get_xtal(void) __attribute__((alias("rtc_clk_xtal_freq_get")));
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