kopia lustrzana https://github.com/espressif/esp-idf
681 wiersze
29 KiB
C
681 wiersze
29 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** SYSTIMER_CONF_REG register
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* Configure system timer clock
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*/
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#define SYSTIMER_CONF_REG (DR_REG_SYSTIMER_BASE + 0x0)
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/** SYSTIMER_SYSTIMER_CLK_FO : R/W; bitpos: [0]; default: 0;
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* systimer clock force on
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*/
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#define SYSTIMER_SYSTIMER_CLK_FO (BIT(0))
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#define SYSTIMER_SYSTIMER_CLK_FO_M (SYSTIMER_SYSTIMER_CLK_FO_V << SYSTIMER_SYSTIMER_CLK_FO_S)
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#define SYSTIMER_SYSTIMER_CLK_FO_V 0x00000001U
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#define SYSTIMER_SYSTIMER_CLK_FO_S 0
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/** SYSTIMER_ETM_EN : R/W; bitpos: [1]; default: 0;
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* Configures whether or not to enable generation of ETM events.\\
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* 0: Disable\\
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* 1: Enable\\
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*/
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#define SYSTIMER_ETM_EN (BIT(1))
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#define SYSTIMER_ETM_EN_M (SYSTIMER_ETM_EN_V << SYSTIMER_ETM_EN_S)
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#define SYSTIMER_ETM_EN_V 0x00000001U
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#define SYSTIMER_ETM_EN_S 1
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/** SYSTIMER_TARGET2_WORK_EN : R/W; bitpos: [22]; default: 0;
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* Configures whether or not to enable COMP2.\\
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* 0: Disable\\
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* 1: Enable\\
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*/
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#define SYSTIMER_TARGET2_WORK_EN (BIT(22))
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#define SYSTIMER_TARGET2_WORK_EN_M (SYSTIMER_TARGET2_WORK_EN_V << SYSTIMER_TARGET2_WORK_EN_S)
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#define SYSTIMER_TARGET2_WORK_EN_V 0x00000001U
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#define SYSTIMER_TARGET2_WORK_EN_S 22
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/** SYSTIMER_TARGET1_WORK_EN : R/W; bitpos: [23]; default: 0;
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* Configures whether or not to enable COMP1. See details in SYSTIMER_TARGET2_WORK_EN.
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*/
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#define SYSTIMER_TARGET1_WORK_EN (BIT(23))
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#define SYSTIMER_TARGET1_WORK_EN_M (SYSTIMER_TARGET1_WORK_EN_V << SYSTIMER_TARGET1_WORK_EN_S)
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#define SYSTIMER_TARGET1_WORK_EN_V 0x00000001U
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#define SYSTIMER_TARGET1_WORK_EN_S 23
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/** SYSTIMER_TARGET0_WORK_EN : R/W; bitpos: [24]; default: 0;
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* Configures whether or not to enable COMP0. See details in SYSTIMER_TARGET2_WORK_EN.
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*/
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#define SYSTIMER_TARGET0_WORK_EN (BIT(24))
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#define SYSTIMER_TARGET0_WORK_EN_M (SYSTIMER_TARGET0_WORK_EN_V << SYSTIMER_TARGET0_WORK_EN_S)
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#define SYSTIMER_TARGET0_WORK_EN_V 0x00000001U
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#define SYSTIMER_TARGET0_WORK_EN_S 24
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/** SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN : R/W; bitpos: [25]; default: 1;
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* Configures whether or not UNIT1 is stalled when CORE1 is stalled. \\
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* 0: UNIT1 is not stalled. \\
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* 1: UNIT1 is stalled.\\
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*/
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#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN (BIT(25))
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#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S)
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#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_V 0x00000001U
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#define SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN_S 25
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/** SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN : R/W; bitpos: [26]; default: 1;
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* Configures whether or not UNIT1 is stalled when CORE0 is stalled. See details in
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* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
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*/
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#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN (BIT(26))
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#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S)
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#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_V 0x00000001U
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#define SYSTIMER_TIMER_UNIT1_CORE0_STALL_EN_S 26
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/** SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN : R/W; bitpos: [27]; default: 0;
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* Configures whether or not UNIT0 is stalled when CORE1 is stalled. See details in
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* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
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*/
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#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN (BIT(27))
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#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S)
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#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_V 0x00000001U
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#define SYSTIMER_TIMER_UNIT0_CORE1_STALL_EN_S 27
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/** SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN : R/W; bitpos: [28]; default: 0;
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* Configures whether or not UNIT0 is stalled when CORE0 is stalled. See details in
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* SYSTIMER_TIMER_UNIT1_CORE1_STALL_EN.
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*/
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#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN (BIT(28))
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#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_M (SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V << SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S)
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#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_V 0x00000001U
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#define SYSTIMER_TIMER_UNIT0_CORE0_STALL_EN_S 28
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/** SYSTIMER_TIMER_UNIT1_WORK_EN : R/W; bitpos: [29]; default: 0;
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* Configures whether or not to enable UNIT1. \\
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* 0: Disable\\
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* 1: Enable\\
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*/
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#define SYSTIMER_TIMER_UNIT1_WORK_EN (BIT(29))
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#define SYSTIMER_TIMER_UNIT1_WORK_EN_M (SYSTIMER_TIMER_UNIT1_WORK_EN_V << SYSTIMER_TIMER_UNIT1_WORK_EN_S)
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#define SYSTIMER_TIMER_UNIT1_WORK_EN_V 0x00000001U
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#define SYSTIMER_TIMER_UNIT1_WORK_EN_S 29
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/** SYSTIMER_TIMER_UNIT0_WORK_EN : R/W; bitpos: [30]; default: 1;
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* Configures whether or not to enable UNIT0. \\
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* 0: Disable\\
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* 1: Enable\\
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*/
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#define SYSTIMER_TIMER_UNIT0_WORK_EN (BIT(30))
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#define SYSTIMER_TIMER_UNIT0_WORK_EN_M (SYSTIMER_TIMER_UNIT0_WORK_EN_V << SYSTIMER_TIMER_UNIT0_WORK_EN_S)
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#define SYSTIMER_TIMER_UNIT0_WORK_EN_V 0x00000001U
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#define SYSTIMER_TIMER_UNIT0_WORK_EN_S 30
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/** SYSTIMER_CLK_EN : R/W; bitpos: [31]; default: 0;
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* Configures register clock gating. \\
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* 0: Only enable needed clock for register read or write operations. \\
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* 1: Register clock is always enabled for read and write operations. \\
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*/
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#define SYSTIMER_CLK_EN (BIT(31))
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#define SYSTIMER_CLK_EN_M (SYSTIMER_CLK_EN_V << SYSTIMER_CLK_EN_S)
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#define SYSTIMER_CLK_EN_V 0x00000001U
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#define SYSTIMER_CLK_EN_S 31
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/** SYSTIMER_UNIT0_OP_REG register
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* Read UNIT0 value to registers
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*/
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#define SYSTIMER_UNIT0_OP_REG (DR_REG_SYSTIMER_BASE + 0x4)
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/** SYSTIMER_TIMER_UNIT0_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
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* Represents UNIT0 value is synchronized and valid.
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*/
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#define SYSTIMER_TIMER_UNIT0_VALUE_VALID (BIT(29))
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#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_M (SYSTIMER_TIMER_UNIT0_VALUE_VALID_V << SYSTIMER_TIMER_UNIT0_VALUE_VALID_S)
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#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_V 0x00000001U
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#define SYSTIMER_TIMER_UNIT0_VALUE_VALID_S 29
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/** SYSTIMER_TIMER_UNIT0_UPDATE : WT; bitpos: [30]; default: 0;
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* Configures whether or not to update timer UNIT0, i.e., reads the UNIT0 count value
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* to SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO. \\
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* 0: No effect\\
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* 1: Update timer UNIT0 \\
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*/
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#define SYSTIMER_TIMER_UNIT0_UPDATE (BIT(30))
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#define SYSTIMER_TIMER_UNIT0_UPDATE_M (SYSTIMER_TIMER_UNIT0_UPDATE_V << SYSTIMER_TIMER_UNIT0_UPDATE_S)
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#define SYSTIMER_TIMER_UNIT0_UPDATE_V 0x00000001U
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#define SYSTIMER_TIMER_UNIT0_UPDATE_S 30
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/** SYSTIMER_UNIT1_OP_REG register
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* Read UNIT1 value to registers
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*/
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#define SYSTIMER_UNIT1_OP_REG (DR_REG_SYSTIMER_BASE + 0x8)
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/** SYSTIMER_TIMER_UNIT1_VALUE_VALID : R/SS/WTC; bitpos: [29]; default: 0;
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* Represents UNIT1 value is synchronized and valid.
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*/
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#define SYSTIMER_TIMER_UNIT1_VALUE_VALID (BIT(29))
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#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_M (SYSTIMER_TIMER_UNIT1_VALUE_VALID_V << SYSTIMER_TIMER_UNIT1_VALUE_VALID_S)
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#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_V 0x00000001U
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#define SYSTIMER_TIMER_UNIT1_VALUE_VALID_S 29
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/** SYSTIMER_TIMER_UNIT1_UPDATE : WT; bitpos: [30]; default: 0;
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* Configures whether or not to update timer UNIT1, i.e., reads the UNIT1 count value
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* to SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO. \\
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* 0: No effect \\
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* 1: Update timer UNIT1\\
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*/
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#define SYSTIMER_TIMER_UNIT1_UPDATE (BIT(30))
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#define SYSTIMER_TIMER_UNIT1_UPDATE_M (SYSTIMER_TIMER_UNIT1_UPDATE_V << SYSTIMER_TIMER_UNIT1_UPDATE_S)
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#define SYSTIMER_TIMER_UNIT1_UPDATE_V 0x00000001U
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#define SYSTIMER_TIMER_UNIT1_UPDATE_S 30
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/** SYSTIMER_UNIT0_LOAD_HI_REG register
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* High 20 bits to be loaded to UNIT0
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*/
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#define SYSTIMER_UNIT0_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0xc)
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/** SYSTIMER_TIMER_UNIT0_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
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* Configures the value to be loaded to UNIT0, high 20 bits.
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*/
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#define SYSTIMER_TIMER_UNIT0_LOAD_HI 0x000FFFFFU
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#define SYSTIMER_TIMER_UNIT0_LOAD_HI_M (SYSTIMER_TIMER_UNIT0_LOAD_HI_V << SYSTIMER_TIMER_UNIT0_LOAD_HI_S)
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#define SYSTIMER_TIMER_UNIT0_LOAD_HI_V 0x000FFFFFU
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#define SYSTIMER_TIMER_UNIT0_LOAD_HI_S 0
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/** SYSTIMER_UNIT0_LOAD_LO_REG register
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* Low 32 bits to be loaded to UNIT0
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*/
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#define SYSTIMER_UNIT0_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x10)
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/** SYSTIMER_TIMER_UNIT0_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
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* Configures the value to be loaded to UNIT0, low 32 bits.
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*/
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#define SYSTIMER_TIMER_UNIT0_LOAD_LO 0xFFFFFFFFU
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#define SYSTIMER_TIMER_UNIT0_LOAD_LO_M (SYSTIMER_TIMER_UNIT0_LOAD_LO_V << SYSTIMER_TIMER_UNIT0_LOAD_LO_S)
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#define SYSTIMER_TIMER_UNIT0_LOAD_LO_V 0xFFFFFFFFU
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#define SYSTIMER_TIMER_UNIT0_LOAD_LO_S 0
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/** SYSTIMER_UNIT1_LOAD_HI_REG register
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* High 20 bits to be loaded to UNIT1
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*/
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#define SYSTIMER_UNIT1_LOAD_HI_REG (DR_REG_SYSTIMER_BASE + 0x14)
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/** SYSTIMER_TIMER_UNIT1_LOAD_HI : R/W; bitpos: [19:0]; default: 0;
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* Configures the value to be loaded to UNIT1, high 20 bits.
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*/
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#define SYSTIMER_TIMER_UNIT1_LOAD_HI 0x000FFFFFU
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#define SYSTIMER_TIMER_UNIT1_LOAD_HI_M (SYSTIMER_TIMER_UNIT1_LOAD_HI_V << SYSTIMER_TIMER_UNIT1_LOAD_HI_S)
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#define SYSTIMER_TIMER_UNIT1_LOAD_HI_V 0x000FFFFFU
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#define SYSTIMER_TIMER_UNIT1_LOAD_HI_S 0
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/** SYSTIMER_UNIT1_LOAD_LO_REG register
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* Low 32 bits to be loaded to UNIT1
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*/
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#define SYSTIMER_UNIT1_LOAD_LO_REG (DR_REG_SYSTIMER_BASE + 0x18)
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/** SYSTIMER_TIMER_UNIT1_LOAD_LO : R/W; bitpos: [31:0]; default: 0;
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* Configures the value to be loaded to UNIT1, low 32 bits.
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*/
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#define SYSTIMER_TIMER_UNIT1_LOAD_LO 0xFFFFFFFFU
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#define SYSTIMER_TIMER_UNIT1_LOAD_LO_M (SYSTIMER_TIMER_UNIT1_LOAD_LO_V << SYSTIMER_TIMER_UNIT1_LOAD_LO_S)
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#define SYSTIMER_TIMER_UNIT1_LOAD_LO_V 0xFFFFFFFFU
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#define SYSTIMER_TIMER_UNIT1_LOAD_LO_S 0
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/** SYSTIMER_TARGET0_HI_REG register
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* Alarm value to be loaded to COMP0, high 20 bits
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*/
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#define SYSTIMER_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x1c)
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/** SYSTIMER_TIMER_TARGET0_HI : R/W; bitpos: [19:0]; default: 0;
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* Configures the alarm value to be loaded to COMP0, high 20 bits.
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*/
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#define SYSTIMER_TIMER_TARGET0_HI 0x000FFFFFU
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#define SYSTIMER_TIMER_TARGET0_HI_M (SYSTIMER_TIMER_TARGET0_HI_V << SYSTIMER_TIMER_TARGET0_HI_S)
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#define SYSTIMER_TIMER_TARGET0_HI_V 0x000FFFFFU
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#define SYSTIMER_TIMER_TARGET0_HI_S 0
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/** SYSTIMER_TARGET0_LO_REG register
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* Alarm value to be loaded to COMP0, low 32 bits
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*/
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#define SYSTIMER_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x20)
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/** SYSTIMER_TIMER_TARGET0_LO : R/W; bitpos: [31:0]; default: 0;
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* Configures the alarm value to be loaded to COMP0, low 32 bits.
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*/
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#define SYSTIMER_TIMER_TARGET0_LO 0xFFFFFFFFU
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#define SYSTIMER_TIMER_TARGET0_LO_M (SYSTIMER_TIMER_TARGET0_LO_V << SYSTIMER_TIMER_TARGET0_LO_S)
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#define SYSTIMER_TIMER_TARGET0_LO_V 0xFFFFFFFFU
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#define SYSTIMER_TIMER_TARGET0_LO_S 0
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/** SYSTIMER_TARGET1_HI_REG register
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* Alarm value to be loaded to COMP1, high 20 bits
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*/
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#define SYSTIMER_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x24)
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/** SYSTIMER_TIMER_TARGET1_HI : R/W; bitpos: [19:0]; default: 0;
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* Configures the alarm value to be loaded to COMP1, high 20 bits.
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*/
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#define SYSTIMER_TIMER_TARGET1_HI 0x000FFFFFU
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#define SYSTIMER_TIMER_TARGET1_HI_M (SYSTIMER_TIMER_TARGET1_HI_V << SYSTIMER_TIMER_TARGET1_HI_S)
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#define SYSTIMER_TIMER_TARGET1_HI_V 0x000FFFFFU
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#define SYSTIMER_TIMER_TARGET1_HI_S 0
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/** SYSTIMER_TARGET1_LO_REG register
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* Alarm value to be loaded to COMP1, low 32 bits
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*/
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#define SYSTIMER_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x28)
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/** SYSTIMER_TIMER_TARGET1_LO : R/W; bitpos: [31:0]; default: 0;
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* Configures the alarm value to be loaded to COMP1, low 32 bits.
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*/
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#define SYSTIMER_TIMER_TARGET1_LO 0xFFFFFFFFU
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#define SYSTIMER_TIMER_TARGET1_LO_M (SYSTIMER_TIMER_TARGET1_LO_V << SYSTIMER_TIMER_TARGET1_LO_S)
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#define SYSTIMER_TIMER_TARGET1_LO_V 0xFFFFFFFFU
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#define SYSTIMER_TIMER_TARGET1_LO_S 0
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/** SYSTIMER_TARGET2_HI_REG register
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* Alarm value to be loaded to COMP2, high 20 bits
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*/
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#define SYSTIMER_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x2c)
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/** SYSTIMER_TIMER_TARGET2_HI : R/W; bitpos: [19:0]; default: 0;
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* Configures the alarm value to be loaded to COMP2, high 20 bits.
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*/
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#define SYSTIMER_TIMER_TARGET2_HI 0x000FFFFFU
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#define SYSTIMER_TIMER_TARGET2_HI_M (SYSTIMER_TIMER_TARGET2_HI_V << SYSTIMER_TIMER_TARGET2_HI_S)
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#define SYSTIMER_TIMER_TARGET2_HI_V 0x000FFFFFU
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#define SYSTIMER_TIMER_TARGET2_HI_S 0
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/** SYSTIMER_TARGET2_LO_REG register
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* Alarm value to be loaded to COMP2, low 32 bits
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*/
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#define SYSTIMER_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x30)
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/** SYSTIMER_TIMER_TARGET2_LO : R/W; bitpos: [31:0]; default: 0;
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* Configures the alarm value to be loaded to COMP2, low 32 bits.
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*/
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#define SYSTIMER_TIMER_TARGET2_LO 0xFFFFFFFFU
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#define SYSTIMER_TIMER_TARGET2_LO_M (SYSTIMER_TIMER_TARGET2_LO_V << SYSTIMER_TIMER_TARGET2_LO_S)
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#define SYSTIMER_TIMER_TARGET2_LO_V 0xFFFFFFFFU
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#define SYSTIMER_TIMER_TARGET2_LO_S 0
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/** SYSTIMER_TARGET0_CONF_REG register
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* Configure COMP0 alarm mode
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*/
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#define SYSTIMER_TARGET0_CONF_REG (DR_REG_SYSTIMER_BASE + 0x34)
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/** SYSTIMER_TARGET0_PERIOD : R/W; bitpos: [25:0]; default: 0;
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* Configures COMP0 alarm period.
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*/
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#define SYSTIMER_TARGET0_PERIOD 0x03FFFFFFU
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#define SYSTIMER_TARGET0_PERIOD_M (SYSTIMER_TARGET0_PERIOD_V << SYSTIMER_TARGET0_PERIOD_S)
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#define SYSTIMER_TARGET0_PERIOD_V 0x03FFFFFFU
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#define SYSTIMER_TARGET0_PERIOD_S 0
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/** SYSTIMER_TARGET0_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
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* Selects the two alarm modes for COMP0. \\
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* 0: Target mode\\
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* 1: Period mode\\
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*/
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#define SYSTIMER_TARGET0_PERIOD_MODE (BIT(30))
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#define SYSTIMER_TARGET0_PERIOD_MODE_M (SYSTIMER_TARGET0_PERIOD_MODE_V << SYSTIMER_TARGET0_PERIOD_MODE_S)
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#define SYSTIMER_TARGET0_PERIOD_MODE_V 0x00000001U
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#define SYSTIMER_TARGET0_PERIOD_MODE_S 30
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/** SYSTIMER_TARGET0_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
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* Chooses the counter value for comparison with COMP0.\\
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* 0: Use the count value from UNIT$0\\
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* 1: Use the count value from UNIT$1\\
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*/
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#define SYSTIMER_TARGET0_TIMER_UNIT_SEL (BIT(31))
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#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_M (SYSTIMER_TARGET0_TIMER_UNIT_SEL_V << SYSTIMER_TARGET0_TIMER_UNIT_SEL_S)
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#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_V 0x00000001U
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#define SYSTIMER_TARGET0_TIMER_UNIT_SEL_S 31
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/** SYSTIMER_TARGET1_CONF_REG register
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* Configure COMP1 alarm mode
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*/
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#define SYSTIMER_TARGET1_CONF_REG (DR_REG_SYSTIMER_BASE + 0x38)
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/** SYSTIMER_TARGET1_PERIOD : R/W; bitpos: [25:0]; default: 0;
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* Configures COMP1 alarm period.
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*/
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#define SYSTIMER_TARGET1_PERIOD 0x03FFFFFFU
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#define SYSTIMER_TARGET1_PERIOD_M (SYSTIMER_TARGET1_PERIOD_V << SYSTIMER_TARGET1_PERIOD_S)
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#define SYSTIMER_TARGET1_PERIOD_V 0x03FFFFFFU
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#define SYSTIMER_TARGET1_PERIOD_S 0
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/** SYSTIMER_TARGET1_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
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* Selects the two alarm modes for COMP1. See details in SYSTIMER_TARGET0_PERIOD_MODE.
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*/
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#define SYSTIMER_TARGET1_PERIOD_MODE (BIT(30))
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#define SYSTIMER_TARGET1_PERIOD_MODE_M (SYSTIMER_TARGET1_PERIOD_MODE_V << SYSTIMER_TARGET1_PERIOD_MODE_S)
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#define SYSTIMER_TARGET1_PERIOD_MODE_V 0x00000001U
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#define SYSTIMER_TARGET1_PERIOD_MODE_S 30
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/** SYSTIMER_TARGET1_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
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* Chooses the counter value for comparison with COMP1. See details in
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* SYSTIMER_TARGET0_TIMER_UNIT_SEL.
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*/
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#define SYSTIMER_TARGET1_TIMER_UNIT_SEL (BIT(31))
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#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_M (SYSTIMER_TARGET1_TIMER_UNIT_SEL_V << SYSTIMER_TARGET1_TIMER_UNIT_SEL_S)
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#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_V 0x00000001U
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#define SYSTIMER_TARGET1_TIMER_UNIT_SEL_S 31
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/** SYSTIMER_TARGET2_CONF_REG register
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* Configure COMP2 alarm mode
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*/
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#define SYSTIMER_TARGET2_CONF_REG (DR_REG_SYSTIMER_BASE + 0x3c)
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/** SYSTIMER_TARGET2_PERIOD : R/W; bitpos: [25:0]; default: 0;
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* Configures COMP2 alarm period.
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*/
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#define SYSTIMER_TARGET2_PERIOD 0x03FFFFFFU
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#define SYSTIMER_TARGET2_PERIOD_M (SYSTIMER_TARGET2_PERIOD_V << SYSTIMER_TARGET2_PERIOD_S)
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#define SYSTIMER_TARGET2_PERIOD_V 0x03FFFFFFU
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#define SYSTIMER_TARGET2_PERIOD_S 0
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/** SYSTIMER_TARGET2_PERIOD_MODE : R/W; bitpos: [30]; default: 0;
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* Configures Configures the two alarm modes for COMP2. See details in
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* SYSTIMER_TARGET0_PERIOD_MODE.
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*/
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#define SYSTIMER_TARGET2_PERIOD_MODE (BIT(30))
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#define SYSTIMER_TARGET2_PERIOD_MODE_M (SYSTIMER_TARGET2_PERIOD_MODE_V << SYSTIMER_TARGET2_PERIOD_MODE_S)
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#define SYSTIMER_TARGET2_PERIOD_MODE_V 0x00000001U
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#define SYSTIMER_TARGET2_PERIOD_MODE_S 30
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/** SYSTIMER_TARGET2_TIMER_UNIT_SEL : R/W; bitpos: [31]; default: 0;
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* Chooses the counter value for comparison with COMP2. See details in
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* SYSTIMER_TARGET0_TIMER_UNIT_SEL.
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*/
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#define SYSTIMER_TARGET2_TIMER_UNIT_SEL (BIT(31))
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#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_M (SYSTIMER_TARGET2_TIMER_UNIT_SEL_V << SYSTIMER_TARGET2_TIMER_UNIT_SEL_S)
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#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_V 0x00000001U
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#define SYSTIMER_TARGET2_TIMER_UNIT_SEL_S 31
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/** SYSTIMER_UNIT0_VALUE_HI_REG register
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* UNIT0 value, high 20 bits
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*/
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#define SYSTIMER_UNIT0_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x40)
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/** SYSTIMER_TIMER_UNIT0_VALUE_HI : RO; bitpos: [19:0]; default: 0;
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* Represents UNIT0 read value, high 20 bits.
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*/
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#define SYSTIMER_TIMER_UNIT0_VALUE_HI 0x000FFFFFU
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#define SYSTIMER_TIMER_UNIT0_VALUE_HI_M (SYSTIMER_TIMER_UNIT0_VALUE_HI_V << SYSTIMER_TIMER_UNIT0_VALUE_HI_S)
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#define SYSTIMER_TIMER_UNIT0_VALUE_HI_V 0x000FFFFFU
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#define SYSTIMER_TIMER_UNIT0_VALUE_HI_S 0
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/** SYSTIMER_UNIT0_VALUE_LO_REG register
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* UNIT0 value, low 32 bits
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*/
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#define SYSTIMER_UNIT0_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x44)
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/** SYSTIMER_TIMER_UNIT0_VALUE_LO : RO; bitpos: [31:0]; default: 0;
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* Represents UNIT0 read value, low 32 bits.
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*/
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#define SYSTIMER_TIMER_UNIT0_VALUE_LO 0xFFFFFFFFU
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#define SYSTIMER_TIMER_UNIT0_VALUE_LO_M (SYSTIMER_TIMER_UNIT0_VALUE_LO_V << SYSTIMER_TIMER_UNIT0_VALUE_LO_S)
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#define SYSTIMER_TIMER_UNIT0_VALUE_LO_V 0xFFFFFFFFU
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#define SYSTIMER_TIMER_UNIT0_VALUE_LO_S 0
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/** SYSTIMER_UNIT1_VALUE_HI_REG register
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* UNIT1 value, high 20 bits
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*/
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#define SYSTIMER_UNIT1_VALUE_HI_REG (DR_REG_SYSTIMER_BASE + 0x48)
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/** SYSTIMER_TIMER_UNIT1_VALUE_HI : RO; bitpos: [19:0]; default: 0;
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* Represents UNIT1 read value, high 20 bits.
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*/
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#define SYSTIMER_TIMER_UNIT1_VALUE_HI 0x000FFFFFU
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#define SYSTIMER_TIMER_UNIT1_VALUE_HI_M (SYSTIMER_TIMER_UNIT1_VALUE_HI_V << SYSTIMER_TIMER_UNIT1_VALUE_HI_S)
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#define SYSTIMER_TIMER_UNIT1_VALUE_HI_V 0x000FFFFFU
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#define SYSTIMER_TIMER_UNIT1_VALUE_HI_S 0
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/** SYSTIMER_UNIT1_VALUE_LO_REG register
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* UNIT1 value, low 32 bits
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*/
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#define SYSTIMER_UNIT1_VALUE_LO_REG (DR_REG_SYSTIMER_BASE + 0x4c)
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/** SYSTIMER_TIMER_UNIT1_VALUE_LO : RO; bitpos: [31:0]; default: 0;
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* Represents UNIT1 read value, low 32 bits.
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*/
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#define SYSTIMER_TIMER_UNIT1_VALUE_LO 0xFFFFFFFFU
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#define SYSTIMER_TIMER_UNIT1_VALUE_LO_M (SYSTIMER_TIMER_UNIT1_VALUE_LO_V << SYSTIMER_TIMER_UNIT1_VALUE_LO_S)
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#define SYSTIMER_TIMER_UNIT1_VALUE_LO_V 0xFFFFFFFFU
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#define SYSTIMER_TIMER_UNIT1_VALUE_LO_S 0
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/** SYSTIMER_COMP0_LOAD_REG register
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* COMP0 synchronization register
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*/
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#define SYSTIMER_COMP0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x50)
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/** SYSTIMER_TIMER_COMP0_LOAD : WT; bitpos: [0]; default: 0;
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* Configures whether or not to enable COMP0 synchronization, i.e., reload the alarm
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* value/period to COMP0.\\
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* 0: No effect \\
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* 1: Enable COMP0 synchronization\\
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*/
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#define SYSTIMER_TIMER_COMP0_LOAD (BIT(0))
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#define SYSTIMER_TIMER_COMP0_LOAD_M (SYSTIMER_TIMER_COMP0_LOAD_V << SYSTIMER_TIMER_COMP0_LOAD_S)
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#define SYSTIMER_TIMER_COMP0_LOAD_V 0x00000001U
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#define SYSTIMER_TIMER_COMP0_LOAD_S 0
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/** SYSTIMER_COMP1_LOAD_REG register
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* COMP1 synchronization register
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*/
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#define SYSTIMER_COMP1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x54)
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/** SYSTIMER_TIMER_COMP1_LOAD : WT; bitpos: [0]; default: 0;
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* Configures whether or not to enable COMP1 synchronization, i.e., reload the alarm
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* value/period to COMP1. \\
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* 0: No effect \\
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* 1: Enable COMP1 synchronization\\
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*/
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#define SYSTIMER_TIMER_COMP1_LOAD (BIT(0))
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#define SYSTIMER_TIMER_COMP1_LOAD_M (SYSTIMER_TIMER_COMP1_LOAD_V << SYSTIMER_TIMER_COMP1_LOAD_S)
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#define SYSTIMER_TIMER_COMP1_LOAD_V 0x00000001U
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#define SYSTIMER_TIMER_COMP1_LOAD_S 0
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/** SYSTIMER_COMP2_LOAD_REG register
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* COMP2 synchronization register
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*/
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#define SYSTIMER_COMP2_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x58)
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/** SYSTIMER_TIMER_COMP2_LOAD : WT; bitpos: [0]; default: 0;
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* Configures whether or not to enable COMP2 synchronization, i.e., reload the alarm
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* value/period to COMP2.\\
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* 0: No effect \\
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* 1: Enable COMP2 synchronization\\
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*/
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#define SYSTIMER_TIMER_COMP2_LOAD (BIT(0))
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#define SYSTIMER_TIMER_COMP2_LOAD_M (SYSTIMER_TIMER_COMP2_LOAD_V << SYSTIMER_TIMER_COMP2_LOAD_S)
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#define SYSTIMER_TIMER_COMP2_LOAD_V 0x00000001U
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#define SYSTIMER_TIMER_COMP2_LOAD_S 0
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/** SYSTIMER_UNIT0_LOAD_REG register
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* UNIT0 synchronization register
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*/
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#define SYSTIMER_UNIT0_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x5c)
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/** SYSTIMER_TIMER_UNIT0_LOAD : WT; bitpos: [0]; default: 0;
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* Configures whether or not to reload the value of UNIT0, i.e., reloads the values of
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* SYSTIMER_TIMER_UNIT0_VALUE_HI and SYSTIMER_TIMER_UNIT0_VALUE_LO to UNIT0. \\
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* 0: No effect \\
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* 1: Reload the value of UNIT0\\
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*/
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#define SYSTIMER_TIMER_UNIT0_LOAD (BIT(0))
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#define SYSTIMER_TIMER_UNIT0_LOAD_M (SYSTIMER_TIMER_UNIT0_LOAD_V << SYSTIMER_TIMER_UNIT0_LOAD_S)
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#define SYSTIMER_TIMER_UNIT0_LOAD_V 0x00000001U
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#define SYSTIMER_TIMER_UNIT0_LOAD_S 0
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/** SYSTIMER_UNIT1_LOAD_REG register
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* UNIT1 synchronization register
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*/
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#define SYSTIMER_UNIT1_LOAD_REG (DR_REG_SYSTIMER_BASE + 0x60)
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/** SYSTIMER_TIMER_UNIT1_LOAD : WT; bitpos: [0]; default: 0;
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* Configures whether or not to reload the value of UNIT1, i.e., reload the values of
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* SYSTIMER_TIMER_UNIT1_VALUE_HI and SYSTIMER_TIMER_UNIT1_VALUE_LO to UNIT1. \\
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* 0: No effect \\
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* 1: Reload the value of UNIT1\\
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*/
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#define SYSTIMER_TIMER_UNIT1_LOAD (BIT(0))
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#define SYSTIMER_TIMER_UNIT1_LOAD_M (SYSTIMER_TIMER_UNIT1_LOAD_V << SYSTIMER_TIMER_UNIT1_LOAD_S)
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#define SYSTIMER_TIMER_UNIT1_LOAD_V 0x00000001U
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#define SYSTIMER_TIMER_UNIT1_LOAD_S 0
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/** SYSTIMER_INT_ENA_REG register
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* Interrupt enable register of system timer
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*/
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#define SYSTIMER_INT_ENA_REG (DR_REG_SYSTIMER_BASE + 0x64)
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/** SYSTIMER_TARGET0_INT_ENA : R/W; bitpos: [0]; default: 0;
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* Write 1 to enable SYSTIMER_TARGET0_INT.
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*/
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#define SYSTIMER_TARGET0_INT_ENA (BIT(0))
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#define SYSTIMER_TARGET0_INT_ENA_M (SYSTIMER_TARGET0_INT_ENA_V << SYSTIMER_TARGET0_INT_ENA_S)
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#define SYSTIMER_TARGET0_INT_ENA_V 0x00000001U
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#define SYSTIMER_TARGET0_INT_ENA_S 0
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/** SYSTIMER_TARGET1_INT_ENA : R/W; bitpos: [1]; default: 0;
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* Write 1 to enable SYSTIMER_TARGET1_INT.
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*/
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#define SYSTIMER_TARGET1_INT_ENA (BIT(1))
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#define SYSTIMER_TARGET1_INT_ENA_M (SYSTIMER_TARGET1_INT_ENA_V << SYSTIMER_TARGET1_INT_ENA_S)
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#define SYSTIMER_TARGET1_INT_ENA_V 0x00000001U
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#define SYSTIMER_TARGET1_INT_ENA_S 1
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/** SYSTIMER_TARGET2_INT_ENA : R/W; bitpos: [2]; default: 0;
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* Write 1 to enable SYSTIMER_TARGET2_INT.
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*/
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#define SYSTIMER_TARGET2_INT_ENA (BIT(2))
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#define SYSTIMER_TARGET2_INT_ENA_M (SYSTIMER_TARGET2_INT_ENA_V << SYSTIMER_TARGET2_INT_ENA_S)
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#define SYSTIMER_TARGET2_INT_ENA_V 0x00000001U
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#define SYSTIMER_TARGET2_INT_ENA_S 2
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/** SYSTIMER_INT_RAW_REG register
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* Interrupt raw register of system timer
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*/
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#define SYSTIMER_INT_RAW_REG (DR_REG_SYSTIMER_BASE + 0x68)
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/** SYSTIMER_TARGET0_INT_RAW : R/WTC/SS; bitpos: [0]; default: 0;
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* The raw interrupt status of SYSTIMER_TARGET0_INT.
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*/
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#define SYSTIMER_TARGET0_INT_RAW (BIT(0))
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#define SYSTIMER_TARGET0_INT_RAW_M (SYSTIMER_TARGET0_INT_RAW_V << SYSTIMER_TARGET0_INT_RAW_S)
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#define SYSTIMER_TARGET0_INT_RAW_V 0x00000001U
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#define SYSTIMER_TARGET0_INT_RAW_S 0
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/** SYSTIMER_TARGET1_INT_RAW : R/WTC/SS; bitpos: [1]; default: 0;
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* The raw interrupt status of SYSTIMER_TARGET1_INT.
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*/
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#define SYSTIMER_TARGET1_INT_RAW (BIT(1))
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#define SYSTIMER_TARGET1_INT_RAW_M (SYSTIMER_TARGET1_INT_RAW_V << SYSTIMER_TARGET1_INT_RAW_S)
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#define SYSTIMER_TARGET1_INT_RAW_V 0x00000001U
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#define SYSTIMER_TARGET1_INT_RAW_S 1
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/** SYSTIMER_TARGET2_INT_RAW : R/WTC/SS; bitpos: [2]; default: 0;
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* The raw interrupt status of SYSTIMER_TARGET2_INT.
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*/
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#define SYSTIMER_TARGET2_INT_RAW (BIT(2))
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#define SYSTIMER_TARGET2_INT_RAW_M (SYSTIMER_TARGET2_INT_RAW_V << SYSTIMER_TARGET2_INT_RAW_S)
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#define SYSTIMER_TARGET2_INT_RAW_V 0x00000001U
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#define SYSTIMER_TARGET2_INT_RAW_S 2
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/** SYSTIMER_INT_CLR_REG register
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* Interrupt clear register of system timer
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*/
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#define SYSTIMER_INT_CLR_REG (DR_REG_SYSTIMER_BASE + 0x6c)
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/** SYSTIMER_TARGET0_INT_CLR : WT; bitpos: [0]; default: 0;
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* Write 1 to clear SYSTIMER_TARGET0_INT.
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*/
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#define SYSTIMER_TARGET0_INT_CLR (BIT(0))
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#define SYSTIMER_TARGET0_INT_CLR_M (SYSTIMER_TARGET0_INT_CLR_V << SYSTIMER_TARGET0_INT_CLR_S)
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#define SYSTIMER_TARGET0_INT_CLR_V 0x00000001U
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#define SYSTIMER_TARGET0_INT_CLR_S 0
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/** SYSTIMER_TARGET1_INT_CLR : WT; bitpos: [1]; default: 0;
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* Write 1 to clear SYSTIMER_TARGET1_INT.
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*/
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#define SYSTIMER_TARGET1_INT_CLR (BIT(1))
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#define SYSTIMER_TARGET1_INT_CLR_M (SYSTIMER_TARGET1_INT_CLR_V << SYSTIMER_TARGET1_INT_CLR_S)
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#define SYSTIMER_TARGET1_INT_CLR_V 0x00000001U
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#define SYSTIMER_TARGET1_INT_CLR_S 1
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/** SYSTIMER_TARGET2_INT_CLR : WT; bitpos: [2]; default: 0;
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* Write 1 to clear SYSTIMER_TARGET2_INT.
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*/
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#define SYSTIMER_TARGET2_INT_CLR (BIT(2))
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#define SYSTIMER_TARGET2_INT_CLR_M (SYSTIMER_TARGET2_INT_CLR_V << SYSTIMER_TARGET2_INT_CLR_S)
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#define SYSTIMER_TARGET2_INT_CLR_V 0x00000001U
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#define SYSTIMER_TARGET2_INT_CLR_S 2
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/** SYSTIMER_INT_ST_REG register
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* Interrupt status register of system timer
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*/
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#define SYSTIMER_INT_ST_REG (DR_REG_SYSTIMER_BASE + 0x70)
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/** SYSTIMER_TARGET0_INT_ST : RO; bitpos: [0]; default: 0;
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* The interrupt status of SYSTIMER_TARGET0_INT.
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*/
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#define SYSTIMER_TARGET0_INT_ST (BIT(0))
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#define SYSTIMER_TARGET0_INT_ST_M (SYSTIMER_TARGET0_INT_ST_V << SYSTIMER_TARGET0_INT_ST_S)
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#define SYSTIMER_TARGET0_INT_ST_V 0x00000001U
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#define SYSTIMER_TARGET0_INT_ST_S 0
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/** SYSTIMER_TARGET1_INT_ST : RO; bitpos: [1]; default: 0;
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* The interrupt status of SYSTIMER_TARGET1_INT.
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*/
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#define SYSTIMER_TARGET1_INT_ST (BIT(1))
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#define SYSTIMER_TARGET1_INT_ST_M (SYSTIMER_TARGET1_INT_ST_V << SYSTIMER_TARGET1_INT_ST_S)
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#define SYSTIMER_TARGET1_INT_ST_V 0x00000001U
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#define SYSTIMER_TARGET1_INT_ST_S 1
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/** SYSTIMER_TARGET2_INT_ST : RO; bitpos: [2]; default: 0;
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* The interrupt status of SYSTIMER_TARGET2_INT.
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*/
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#define SYSTIMER_TARGET2_INT_ST (BIT(2))
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#define SYSTIMER_TARGET2_INT_ST_M (SYSTIMER_TARGET2_INT_ST_V << SYSTIMER_TARGET2_INT_ST_S)
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#define SYSTIMER_TARGET2_INT_ST_V 0x00000001U
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#define SYSTIMER_TARGET2_INT_ST_S 2
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/** SYSTIMER_REAL_TARGET0_LO_REG register
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* Actual target value of COMP0, low 32 bits
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*/
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#define SYSTIMER_REAL_TARGET0_LO_REG (DR_REG_SYSTIMER_BASE + 0x74)
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/** SYSTIMER_TARGET0_LO_RO : RO; bitpos: [31:0]; default: 0;
|
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* Represents the actual target value of COMP0, low 32 bits.
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*/
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#define SYSTIMER_TARGET0_LO_RO 0xFFFFFFFFU
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#define SYSTIMER_TARGET0_LO_RO_M (SYSTIMER_TARGET0_LO_RO_V << SYSTIMER_TARGET0_LO_RO_S)
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#define SYSTIMER_TARGET0_LO_RO_V 0xFFFFFFFFU
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#define SYSTIMER_TARGET0_LO_RO_S 0
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/** SYSTIMER_REAL_TARGET0_HI_REG register
|
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* Actual target value of COMP0, high 20 bits
|
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*/
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#define SYSTIMER_REAL_TARGET0_HI_REG (DR_REG_SYSTIMER_BASE + 0x78)
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/** SYSTIMER_TARGET0_HI_RO : RO; bitpos: [19:0]; default: 0;
|
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* Represents the actual target value of COMP0, high 20 bits.
|
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*/
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#define SYSTIMER_TARGET0_HI_RO 0x000FFFFFU
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#define SYSTIMER_TARGET0_HI_RO_M (SYSTIMER_TARGET0_HI_RO_V << SYSTIMER_TARGET0_HI_RO_S)
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#define SYSTIMER_TARGET0_HI_RO_V 0x000FFFFFU
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#define SYSTIMER_TARGET0_HI_RO_S 0
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/** SYSTIMER_REAL_TARGET1_LO_REG register
|
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* Actual target value of COMP1, low 32 bits
|
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*/
|
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#define SYSTIMER_REAL_TARGET1_LO_REG (DR_REG_SYSTIMER_BASE + 0x7c)
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/** SYSTIMER_TARGET1_LO_RO : RO; bitpos: [31:0]; default: 0;
|
|
* Represents the actual target value of COMP1, low 32 bits.
|
|
*/
|
|
#define SYSTIMER_TARGET1_LO_RO 0xFFFFFFFFU
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#define SYSTIMER_TARGET1_LO_RO_M (SYSTIMER_TARGET1_LO_RO_V << SYSTIMER_TARGET1_LO_RO_S)
|
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#define SYSTIMER_TARGET1_LO_RO_V 0xFFFFFFFFU
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#define SYSTIMER_TARGET1_LO_RO_S 0
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|
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/** SYSTIMER_REAL_TARGET1_HI_REG register
|
|
* Actual target value of COMP1, high 20 bits
|
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*/
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#define SYSTIMER_REAL_TARGET1_HI_REG (DR_REG_SYSTIMER_BASE + 0x80)
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/** SYSTIMER_TARGET1_HI_RO : RO; bitpos: [19:0]; default: 0;
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* Represents the actual target value of COMP1, high 20 bits.
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*/
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#define SYSTIMER_TARGET1_HI_RO 0x000FFFFFU
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#define SYSTIMER_TARGET1_HI_RO_M (SYSTIMER_TARGET1_HI_RO_V << SYSTIMER_TARGET1_HI_RO_S)
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#define SYSTIMER_TARGET1_HI_RO_V 0x000FFFFFU
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#define SYSTIMER_TARGET1_HI_RO_S 0
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/** SYSTIMER_REAL_TARGET2_LO_REG register
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* Actual target value of COMP2, low 32 bits
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*/
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#define SYSTIMER_REAL_TARGET2_LO_REG (DR_REG_SYSTIMER_BASE + 0x84)
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/** SYSTIMER_TARGET2_LO_RO : RO; bitpos: [31:0]; default: 0;
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* Represents the actual target value of COMP2, low 32 bits.
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*/
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#define SYSTIMER_TARGET2_LO_RO 0xFFFFFFFFU
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#define SYSTIMER_TARGET2_LO_RO_M (SYSTIMER_TARGET2_LO_RO_V << SYSTIMER_TARGET2_LO_RO_S)
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#define SYSTIMER_TARGET2_LO_RO_V 0xFFFFFFFFU
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#define SYSTIMER_TARGET2_LO_RO_S 0
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/** SYSTIMER_REAL_TARGET2_HI_REG register
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* Actual target value of COMP2, high 20 bits
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*/
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#define SYSTIMER_REAL_TARGET2_HI_REG (DR_REG_SYSTIMER_BASE + 0x88)
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/** SYSTIMER_TARGET2_HI_RO : RO; bitpos: [19:0]; default: 0;
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* Represents the actual target value of COMP2, high 20 bits.
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*/
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#define SYSTIMER_TARGET2_HI_RO 0x000FFFFFU
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#define SYSTIMER_TARGET2_HI_RO_M (SYSTIMER_TARGET2_HI_RO_V << SYSTIMER_TARGET2_HI_RO_S)
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#define SYSTIMER_TARGET2_HI_RO_V 0x000FFFFFU
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#define SYSTIMER_TARGET2_HI_RO_S 0
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/** SYSTIMER_DATE_REG register
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* Version control register
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*/
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#define SYSTIMER_DATE_REG (DR_REG_SYSTIMER_BASE + 0xfc)
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/** SYSTIMER_DATE : R/W; bitpos: [31:0]; default: 36774432;
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* Version control register.
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*/
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#define SYSTIMER_DATE 0xFFFFFFFFU
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#define SYSTIMER_DATE_M (SYSTIMER_DATE_V << SYSTIMER_DATE_S)
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#define SYSTIMER_DATE_V 0xFFFFFFFFU
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#define SYSTIMER_DATE_S 0
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#ifdef __cplusplus
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}
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#endif
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