kopia lustrzana https://github.com/espressif/esp-idf
250 wiersze
9.4 KiB
C
250 wiersze
9.4 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "soc/soc.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** LP_ANA_BOD_MODE0_CNTL_REG register
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* Configure brownout mode0
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*/
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#define LP_ANA_BOD_MODE0_CNTL_REG (DR_REG_LP_ANA_BASE + 0x0)
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/** LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA : R/W; bitpos: [6]; default: 0;
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* enable suspend spi when brownout interrupt or not
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* 1:enable
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* 0:disable
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*/
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#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA (BIT(6))
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#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_M (LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V << LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S)
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#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_V 0x00000001U
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#define LP_ANA_BOD_MODE0_CLOSE_FLASH_ENA_S 6
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/** LP_ANA_BOD_MODE0_PD_RF_ENA : R/W; bitpos: [7]; default: 0;
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* enable power down RF when brownout interrupt or not
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* 1:enable
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* 0:disable
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*/
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#define LP_ANA_BOD_MODE0_PD_RF_ENA (BIT(7))
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#define LP_ANA_BOD_MODE0_PD_RF_ENA_M (LP_ANA_BOD_MODE0_PD_RF_ENA_V << LP_ANA_BOD_MODE0_PD_RF_ENA_S)
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#define LP_ANA_BOD_MODE0_PD_RF_ENA_V 0x00000001U
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#define LP_ANA_BOD_MODE0_PD_RF_ENA_S 7
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/** LP_ANA_BOD_MODE0_INTR_WAIT : R/W; bitpos: [17:8]; default: 1;
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* set the undervoltage hold time for triggering brownout interrupt
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*/
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#define LP_ANA_BOD_MODE0_INTR_WAIT 0x000003FFU
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#define LP_ANA_BOD_MODE0_INTR_WAIT_M (LP_ANA_BOD_MODE0_INTR_WAIT_V << LP_ANA_BOD_MODE0_INTR_WAIT_S)
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#define LP_ANA_BOD_MODE0_INTR_WAIT_V 0x000003FFU
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#define LP_ANA_BOD_MODE0_INTR_WAIT_S 8
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/** LP_ANA_BOD_MODE0_RESET_WAIT : R/W; bitpos: [27:18]; default: 1023;
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* set the undervoltage hold time for triggering brownout reset
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*/
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#define LP_ANA_BOD_MODE0_RESET_WAIT 0x000003FFU
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#define LP_ANA_BOD_MODE0_RESET_WAIT_M (LP_ANA_BOD_MODE0_RESET_WAIT_V << LP_ANA_BOD_MODE0_RESET_WAIT_S)
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#define LP_ANA_BOD_MODE0_RESET_WAIT_V 0x000003FFU
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#define LP_ANA_BOD_MODE0_RESET_WAIT_S 18
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/** LP_ANA_BOD_MODE0_CNT_CLR : R/W; bitpos: [28]; default: 0;
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* clear brownout count or not
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* 1: clear
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* 0: no operation
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*/
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#define LP_ANA_BOD_MODE0_CNT_CLR (BIT(28))
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#define LP_ANA_BOD_MODE0_CNT_CLR_M (LP_ANA_BOD_MODE0_CNT_CLR_V << LP_ANA_BOD_MODE0_CNT_CLR_S)
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#define LP_ANA_BOD_MODE0_CNT_CLR_V 0x00000001U
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#define LP_ANA_BOD_MODE0_CNT_CLR_S 28
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/** LP_ANA_BOD_MODE0_INTR_ENA : R/W; bitpos: [29]; default: 0;
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* enable brownout interrupt or not
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* 1: enable
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* 0: disable
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*/
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#define LP_ANA_BOD_MODE0_INTR_ENA (BIT(29))
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#define LP_ANA_BOD_MODE0_INTR_ENA_M (LP_ANA_BOD_MODE0_INTR_ENA_V << LP_ANA_BOD_MODE0_INTR_ENA_S)
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#define LP_ANA_BOD_MODE0_INTR_ENA_V 0x00000001U
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#define LP_ANA_BOD_MODE0_INTR_ENA_S 29
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/** LP_ANA_BOD_MODE0_RESET_SEL : R/W; bitpos: [30]; default: 0;
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* select brownout reset level
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* 1: system reset
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* 0: chip reset
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*/
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#define LP_ANA_BOD_MODE0_RESET_SEL (BIT(30))
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#define LP_ANA_BOD_MODE0_RESET_SEL_M (LP_ANA_BOD_MODE0_RESET_SEL_V << LP_ANA_BOD_MODE0_RESET_SEL_S)
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#define LP_ANA_BOD_MODE0_RESET_SEL_V 0x00000001U
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#define LP_ANA_BOD_MODE0_RESET_SEL_S 30
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/** LP_ANA_BOD_MODE0_RESET_ENA : R/W; bitpos: [31]; default: 0;
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* enable brownout reset or not
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* 1: enable
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* 0: disable
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*/
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#define LP_ANA_BOD_MODE0_RESET_ENA (BIT(31))
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#define LP_ANA_BOD_MODE0_RESET_ENA_M (LP_ANA_BOD_MODE0_RESET_ENA_V << LP_ANA_BOD_MODE0_RESET_ENA_S)
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#define LP_ANA_BOD_MODE0_RESET_ENA_V 0x00000001U
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#define LP_ANA_BOD_MODE0_RESET_ENA_S 31
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/** LP_ANA_BOD_MODE1_CNTL_REG register
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* Configure brownout mode1
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*/
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#define LP_ANA_BOD_MODE1_CNTL_REG (DR_REG_LP_ANA_BASE + 0x4)
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/** LP_ANA_BOD_MODE1_RESET_ENA : R/W; bitpos: [31]; default: 0;
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* enable brownout mode1 reset or not
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* 1: enable
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* 0: disable
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*/
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#define LP_ANA_BOD_MODE1_RESET_ENA (BIT(31))
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#define LP_ANA_BOD_MODE1_RESET_ENA_M (LP_ANA_BOD_MODE1_RESET_ENA_V << LP_ANA_BOD_MODE1_RESET_ENA_S)
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#define LP_ANA_BOD_MODE1_RESET_ENA_V 0x00000001U
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#define LP_ANA_BOD_MODE1_RESET_ENA_S 31
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/** LP_ANA_CK_GLITCH_CNTL_REG register
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* Configure power glitch
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*/
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#define LP_ANA_CK_GLITCH_CNTL_REG (DR_REG_LP_ANA_BASE + 0x8)
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/** LP_ANA_PWR_GLITCH_RESET_ENA : R/W; bitpos: [30:27]; default: 0;
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* enable powerglitch or not
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*/
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#define LP_ANA_PWR_GLITCH_RESET_ENA 0x0000000FU
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#define LP_ANA_PWR_GLITCH_RESET_ENA_M (LP_ANA_PWR_GLITCH_RESET_ENA_V << LP_ANA_PWR_GLITCH_RESET_ENA_S)
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#define LP_ANA_PWR_GLITCH_RESET_ENA_V 0x0000000FU
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#define LP_ANA_PWR_GLITCH_RESET_ENA_S 27
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/** LP_ANA_CK_GLITCH_RESET_ENA : R/W; bitpos: [31]; default: 0;
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* reserved
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*/
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#define LP_ANA_CK_GLITCH_RESET_ENA (BIT(31))
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#define LP_ANA_CK_GLITCH_RESET_ENA_M (LP_ANA_CK_GLITCH_RESET_ENA_V << LP_ANA_CK_GLITCH_RESET_ENA_S)
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#define LP_ANA_CK_GLITCH_RESET_ENA_V 0x00000001U
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#define LP_ANA_CK_GLITCH_RESET_ENA_S 31
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/** LP_ANA_FIB_ENABLE_REG register
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* configure FIB REG
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*/
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#define LP_ANA_FIB_ENABLE_REG (DR_REG_LP_ANA_BASE + 0xc)
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/** LP_ANA_ANA_FIB_ENA : R/W; bitpos: [31:0]; default: 4294967295;
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* configure analog fib by software
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*/
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#define LP_ANA_ANA_FIB_ENA 0xFFFFFFFFU
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#define LP_ANA_ANA_FIB_ENA_M (LP_ANA_ANA_FIB_ENA_V << LP_ANA_ANA_FIB_ENA_S)
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#define LP_ANA_ANA_FIB_ENA_V 0xFFFFFFFFU
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#define LP_ANA_ANA_FIB_ENA_S 0
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/** LP_ANA_INT_RAW_REG register
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* interrpt raw register
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*/
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#define LP_ANA_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x10)
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/** LP_ANA_BOD_MODE0_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
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* brownout mode0 interrupt raw register
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*/
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#define LP_ANA_BOD_MODE0_INT_RAW (BIT(31))
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#define LP_ANA_BOD_MODE0_INT_RAW_M (LP_ANA_BOD_MODE0_INT_RAW_V << LP_ANA_BOD_MODE0_INT_RAW_S)
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#define LP_ANA_BOD_MODE0_INT_RAW_V 0x00000001U
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#define LP_ANA_BOD_MODE0_INT_RAW_S 31
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/** LP_ANA_INT_ST_REG register
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* interrpt status register
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*/
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#define LP_ANA_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x14)
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/** LP_ANA_BOD_MODE0_INT_ST : RO; bitpos: [31]; default: 0;
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* brownout mode0 interrupt status register
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*/
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#define LP_ANA_BOD_MODE0_INT_ST (BIT(31))
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#define LP_ANA_BOD_MODE0_INT_ST_M (LP_ANA_BOD_MODE0_INT_ST_V << LP_ANA_BOD_MODE0_INT_ST_S)
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#define LP_ANA_BOD_MODE0_INT_ST_V 0x00000001U
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#define LP_ANA_BOD_MODE0_INT_ST_S 31
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/** LP_ANA_INT_ENA_REG register
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* interrpt enable register
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*/
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#define LP_ANA_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x18)
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/** LP_ANA_BOD_MODE0_INT_ENA : R/W; bitpos: [31]; default: 0;
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* brownout mode0 interrupt enable register
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*/
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#define LP_ANA_BOD_MODE0_INT_ENA (BIT(31))
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#define LP_ANA_BOD_MODE0_INT_ENA_M (LP_ANA_BOD_MODE0_INT_ENA_V << LP_ANA_BOD_MODE0_INT_ENA_S)
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#define LP_ANA_BOD_MODE0_INT_ENA_V 0x00000001U
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#define LP_ANA_BOD_MODE0_INT_ENA_S 31
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/** LP_ANA_INT_CLR_REG register
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* interrpt clear register
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*/
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#define LP_ANA_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x1c)
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/** LP_ANA_BOD_MODE0_INT_CLR : WT; bitpos: [31]; default: 0;
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* brownout mode0 interrupt clear register
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*/
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#define LP_ANA_BOD_MODE0_INT_CLR (BIT(31))
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#define LP_ANA_BOD_MODE0_INT_CLR_M (LP_ANA_BOD_MODE0_INT_CLR_V << LP_ANA_BOD_MODE0_INT_CLR_S)
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#define LP_ANA_BOD_MODE0_INT_CLR_V 0x00000001U
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#define LP_ANA_BOD_MODE0_INT_CLR_S 31
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/** LP_ANA_LP_INT_RAW_REG register
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* lp interrupt raw register
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*/
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#define LP_ANA_LP_INT_RAW_REG (DR_REG_LP_ANA_BASE + 0x20)
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/** LP_ANA_BOD_MODE0_LP_INT_RAW : R/WTC/SS; bitpos: [31]; default: 0;
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* brownout mode0 lp interrupt raw register
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*/
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#define LP_ANA_BOD_MODE0_LP_INT_RAW (BIT(31))
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#define LP_ANA_BOD_MODE0_LP_INT_RAW_M (LP_ANA_BOD_MODE0_LP_INT_RAW_V << LP_ANA_BOD_MODE0_LP_INT_RAW_S)
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#define LP_ANA_BOD_MODE0_LP_INT_RAW_V 0x00000001U
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#define LP_ANA_BOD_MODE0_LP_INT_RAW_S 31
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/** LP_ANA_LP_INT_ST_REG register
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* lp interrupt status register
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*/
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#define LP_ANA_LP_INT_ST_REG (DR_REG_LP_ANA_BASE + 0x24)
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/** LP_ANA_BOD_MODE0_LP_INT_ST : RO; bitpos: [31]; default: 0;
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* brownout mode0 lp interrupt status register
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*/
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#define LP_ANA_BOD_MODE0_LP_INT_ST (BIT(31))
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#define LP_ANA_BOD_MODE0_LP_INT_ST_M (LP_ANA_BOD_MODE0_LP_INT_ST_V << LP_ANA_BOD_MODE0_LP_INT_ST_S)
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#define LP_ANA_BOD_MODE0_LP_INT_ST_V 0x00000001U
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#define LP_ANA_BOD_MODE0_LP_INT_ST_S 31
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/** LP_ANA_LP_INT_ENA_REG register
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* lp interrupt enable register
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*/
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#define LP_ANA_LP_INT_ENA_REG (DR_REG_LP_ANA_BASE + 0x28)
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/** LP_ANA_BOD_MODE0_LP_INT_ENA : R/W; bitpos: [31]; default: 0;
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* brownout mode0 lp interrupt enable register
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*/
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#define LP_ANA_BOD_MODE0_LP_INT_ENA (BIT(31))
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#define LP_ANA_BOD_MODE0_LP_INT_ENA_M (LP_ANA_BOD_MODE0_LP_INT_ENA_V << LP_ANA_BOD_MODE0_LP_INT_ENA_S)
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#define LP_ANA_BOD_MODE0_LP_INT_ENA_V 0x00000001U
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#define LP_ANA_BOD_MODE0_LP_INT_ENA_S 31
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/** LP_ANA_LP_INT_CLR_REG register
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* lp interrupt clear register
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*/
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#define LP_ANA_LP_INT_CLR_REG (DR_REG_LP_ANA_BASE + 0x2c)
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/** LP_ANA_BOD_MODE0_LP_INT_CLR : WT; bitpos: [31]; default: 0;
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* brownout mode0 lp interrupt clear register
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*/
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#define LP_ANA_BOD_MODE0_LP_INT_CLR (BIT(31))
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#define LP_ANA_BOD_MODE0_LP_INT_CLR_M (LP_ANA_BOD_MODE0_LP_INT_CLR_V << LP_ANA_BOD_MODE0_LP_INT_CLR_S)
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#define LP_ANA_BOD_MODE0_LP_INT_CLR_V 0x00000001U
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#define LP_ANA_BOD_MODE0_LP_INT_CLR_S 31
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/** LP_ANA_DATE_REG register
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* version register
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*/
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#define LP_ANA_DATE_REG (DR_REG_LP_ANA_BASE + 0x3fc)
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/** LP_ANA_LP_ANA_DATE : R/W; bitpos: [30:0]; default: 36774528;
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* version register
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*/
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#define LP_ANA_LP_ANA_DATE 0x7FFFFFFFU
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#define LP_ANA_LP_ANA_DATE_M (LP_ANA_LP_ANA_DATE_V << LP_ANA_LP_ANA_DATE_S)
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#define LP_ANA_LP_ANA_DATE_V 0x7FFFFFFFU
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#define LP_ANA_LP_ANA_DATE_S 0
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/** LP_ANA_CLK_EN : R/W; bitpos: [31]; default: 0;
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* reserved
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*/
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#define LP_ANA_CLK_EN (BIT(31))
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#define LP_ANA_CLK_EN_M (LP_ANA_CLK_EN_V << LP_ANA_CLK_EN_S)
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#define LP_ANA_CLK_EN_V 0x00000001U
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#define LP_ANA_CLK_EN_S 31
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#ifdef __cplusplus
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}
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#endif
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