esp-idf/components/hal/esp32s2/efuse_hal.c

68 wiersze
1.7 KiB
C

/*
* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
*
* SPDX-License-Identifier: Apache-2.0
*/
#include "sdkconfig.h"
#include <sys/param.h>
#include "soc/soc_caps.h"
#include "hal/assert.h"
#include "hal/efuse_hal.h"
#include "hal/efuse_ll.h"
#include "esp32s2/rom/efuse.h"
#define ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block) ((error_reg) & (0x0F << (4 * (block))))
uint32_t efuse_hal_get_chip_revision(void)
{
return efuse_ll_get_chip_revision();
}
/******************* eFuse control functions *************************/
void efuse_hal_set_timing(uint32_t apb_freq_hz)
{
ets_efuse_set_timing(apb_freq_hz);
}
void efuse_hal_read(void)
{
ets_efuse_read();
}
void efuse_hal_clear_program_registers(void)
{
ets_efuse_clear_program_registers();
}
void efuse_hal_program(uint32_t block)
{
ets_efuse_program(block);
}
void efuse_hal_rs_calculate(const void *data, void *rs_values)
{
ets_efuse_rs_calculate(data, rs_values);
}
/******************* eFuse control functions *************************/
bool efuse_hal_is_coding_error_in_block(unsigned block)
{
if (block == 0) {
for (unsigned i = 0; i < 5; i++) {
if (REG_READ(EFUSE_RD_REPEAT_ERR0_REG + i * 4)) {
return true;
}
}
} else if (block <= 10) {
// EFUSE_RD_RS_ERR0_REG: (hi) BLOCK8, BLOCK7, BLOCK6, BLOCK5, BLOCK4, BLOCK3, BLOCK2, BLOCK1 (low)
// EFUSE_RD_RS_ERR1_REG: BLOCK10, BLOCK9
block--;
uint32_t error_reg = REG_READ(EFUSE_RD_RS_ERR0_REG + (block / 8) * 4);
return ESP_EFUSE_BLOCK_ERROR_BITS(error_reg, block % 8) != 0;
}
return false;
}