kopia lustrzana https://github.com/espressif/esp-idf
79 wiersze
2.9 KiB
C
79 wiersze
2.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/*
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The cache has an interrupt that can be raised as soon as an access to a cached
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region (flash) is done without the cache being enabled. We use that here
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to panic the CPU, which from a debugging perspective is better than grabbing bad
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data from the bus.
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*/
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#include "esp_rom_sys.h"
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#include "esp_attr.h"
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#include "esp_log.h"
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#include "esp_intr_alloc.h"
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#include "soc/periph_defs.h"
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#include "riscv/interrupt.h"
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#include "hal/cache_ll.h"
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static const char *TAG = "CACHE_ERR";
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void esp_cache_err_int_init(void)
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{
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const uint32_t core_id = 0;
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/* Disable cache interrupts if enabled. */
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ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
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/**
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* Bind all cache errors to ETS_CACHEERR_INUM interrupt. we will deal with
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* them in handler by different types
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* I) Cache access error
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* 1. dbus trying to write to icache
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* 2. dbus authentication fail
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* 3. cpu access icache while dbus is disabled [1]
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* 4. ibus authentication fail
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* 5. ibus trying to write icache
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* 6. cpu access icache while ibus is disabled
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* II) Cache illegal error
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* 1. dbus counter overflow
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* 2. ibus counter overflow
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* 3. mmu entry fault
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* 4. icache preload configurations fault
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* 5. icache sync configuration fault
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*
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* [1]: On ESP32-C2 boards, the caches are shared but buses are still
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* distinct. So, we have an ibus and a dbus sharing the same cache.
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* This error can occur if the dbus performs a request but the icache
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* (or simply cache) is disabled.
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*/
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esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
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esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
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/* Set the type and priority to cache error interrupts. */
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esprv_intc_int_set_type(BIT(ETS_CACHEERR_INUM), INTR_TYPE_LEVEL);
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esprv_intc_int_set_priority(ETS_CACHEERR_INUM, SOC_INTERRUPT_LEVEL_MEDIUM);
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ESP_DRAM_LOGV(TAG, "access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
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/* On the hardware side, start by clearing all the bits reponsible for cache access error */
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cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
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/* Then enable cache access error interrupts. */
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cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
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/* Same goes for cache illegal error: start by clearing the bits and then
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* set them back. */
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ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK);
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cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK);
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cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK);
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/* Enable the interrupts for cache error. */
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ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
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}
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int IRAM_ATTR esp_cache_err_get_cpuid(void)
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{
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return 0;
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}
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