kopia lustrzana https://github.com/espressif/esp-idf
126 wiersze
5.1 KiB
C
126 wiersze
5.1 KiB
C
/*
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* SPDX-FileCopyrightText: 2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file cache_err_int.c
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* @brief The cache has an interrupt that can be raised as soon as an access to a cached
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* region (Flash, PSRAM) is done without the cache being enabled.
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* We use that here to panic the CPU, which from a debugging perspective,
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* is better than grabbing bad data from the bus.
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*/
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_attr.h"
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#include "esp_intr_alloc.h"
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#include "soc/soc.h"
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#include "soc/extmem_reg.h"
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#include "soc/periph_defs.h"
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#include "hal/cpu_hal.h"
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#include "esp32s3/dport_access.h"
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#include "esp32s3/rom/ets_sys.h"
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void esp_cache_err_int_init(void)
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{
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uint32_t core_id = cpu_hal_get_core_id();
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ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
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// We do not register a handler for the interrupt because it is interrupt
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// level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
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// a call to the panic handler for this interrupt.
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intr_matrix_set(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
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// Enable invalid cache access interrupt when the cache is disabled.
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// When the interrupt happens, we can not determine the CPU where the
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// invalid cache access has occurred. We enable the interrupt to catch
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// invalid access on both CPUs, but the interrupt is connected to the
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// CPU which happens to call this function.
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// For this reason, panic handler backtrace will not be correct if the
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// interrupt is connected to PRO CPU and invalid access happens on the APP CPU.
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SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_CLR_REG,
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EXTMEM_MMU_ENTRY_FAULT_INT_CLR |
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EXTMEM_DCACHE_WRITE_FLASH_INT_CLR |
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EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_CLR |
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EXTMEM_DCACHE_SYNC_OP_FAULT_INT_CLR |
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EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_CLR |
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EXTMEM_ICACHE_SYNC_OP_FAULT_INT_CLR);
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SET_PERI_REG_MASK(EXTMEM_CACHE_ILG_INT_ENA_REG,
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EXTMEM_MMU_ENTRY_FAULT_INT_ENA |
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EXTMEM_DCACHE_WRITE_FLASH_INT_ENA |
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EXTMEM_DCACHE_PRELOAD_OP_FAULT_INT_ENA |
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EXTMEM_DCACHE_SYNC_OP_FAULT_INT_ENA |
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EXTMEM_ICACHE_PRELOAD_OP_FAULT_INT_ENA |
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EXTMEM_ICACHE_SYNC_OP_FAULT_INT_ENA);
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if (core_id == PRO_CPU_NUM) {
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intr_matrix_set(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
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/* On the hardware side, stat by clearing all the bits reponsible for
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* enabling cache access error interrupts. */
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SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_CLR_REG,
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EXTMEM_CORE0_DBUS_REJECT_INT_CLR |
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EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_CLR |
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EXTMEM_CORE0_IBUS_REJECT_INT_CLR |
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EXTMEM_CORE0_IBUS_WR_IC_INT_CLR |
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EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_CLR);
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/* Enable cache access error interrupts */
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SET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ENA_REG,
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EXTMEM_CORE0_DBUS_REJECT_INT_ENA |
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EXTMEM_CORE0_DBUS_ACS_MSK_DC_INT_ENA |
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EXTMEM_CORE0_IBUS_REJECT_INT_ENA |
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EXTMEM_CORE0_IBUS_WR_IC_INT_ENA |
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EXTMEM_CORE0_IBUS_ACS_MSK_IC_INT_ENA);
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} else {
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intr_matrix_set(core_id, ETS_CACHE_CORE1_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
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/* On the hardware side, stat by clearing all the bits reponsible for
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* enabling cache access error interrupts. */
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SET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_CLR_REG,
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EXTMEM_CORE1_DBUS_REJECT_INT_CLR |
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EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_CLR |
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EXTMEM_CORE1_IBUS_REJECT_INT_CLR |
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EXTMEM_CORE1_IBUS_WR_IC_INT_CLR |
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EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_CLR);
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/* Enable cache access error interrupts */
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SET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ENA_REG,
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EXTMEM_CORE1_DBUS_REJECT_INT_ENA |
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EXTMEM_CORE1_DBUS_ACS_MSK_DC_INT_ENA |
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EXTMEM_CORE1_IBUS_REJECT_INT_ENA |
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EXTMEM_CORE1_IBUS_WR_IC_INT_ENA |
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EXTMEM_CORE1_IBUS_ACS_MSK_IC_INT_ENA);
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}
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ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
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}
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int IRAM_ATTR esp_cache_err_get_cpuid(void)
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{
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const uint32_t pro_mask = EXTMEM_CORE0_DBUS_REJECT_ST |
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EXTMEM_CORE0_DBUS_ACS_MSK_DCACHE_ST |
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EXTMEM_CORE0_IBUS_REJECT_ST |
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EXTMEM_CORE0_IBUS_WR_ICACHE_ST |
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EXTMEM_CORE0_IBUS_ACS_MSK_ICACHE_ST;
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if (GET_PERI_REG_MASK(EXTMEM_CORE0_ACS_CACHE_INT_ST_REG, pro_mask)) {
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return PRO_CPU_NUM;
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}
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const uint32_t app_mask = EXTMEM_CORE1_DBUS_REJECT_ST |
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EXTMEM_CORE1_DBUS_ACS_MSK_DCACHE_ST |
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EXTMEM_CORE1_IBUS_REJECT_ST |
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EXTMEM_CORE1_IBUS_WR_ICACHE_ST |
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EXTMEM_CORE1_IBUS_ACS_MSK_ICACHE_ST;
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if (GET_PERI_REG_MASK(EXTMEM_CORE1_ACS_CACHE_INT_ST_REG, app_mask)) {
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return APP_CPU_NUM;
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}
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return -1;
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}
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