kopia lustrzana https://github.com/espressif/esp-idf
61 wiersze
1.6 KiB
C
61 wiersze
1.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "bootloader_common.h"
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#include "bootloader_clock.h"
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#include "soc/efuse_reg.h"
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#include "soc/syscon_reg.h"
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uint8_t bootloader_common_get_chip_revision(void)
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{
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uint8_t eco_bit0, eco_bit1, eco_bit2;
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eco_bit0 = (REG_READ(EFUSE_BLK0_RDATA3_REG) & 0xF000) >> 15;
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eco_bit1 = (REG_READ(EFUSE_BLK0_RDATA5_REG) & 0x100000) >> 20;
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eco_bit2 = (REG_READ(SYSCON_DATE_REG) & 0x80000000) >> 31;
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uint32_t combine_value = (eco_bit2 << 2) | (eco_bit1 << 1) | eco_bit0;
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uint8_t chip_ver = 0;
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switch (combine_value) {
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case 0:
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chip_ver = 0;
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break;
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case 1:
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chip_ver = 1;
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break;
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case 3:
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chip_ver = 2;
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break;
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#if CONFIG_IDF_ENV_FPGA
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case 4: /* Empty efuses, but SYSCON_DATE_REG bit is set */
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chip_ver = 3;
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break;
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#endif
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case 7:
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chip_ver = 3;
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break;
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default:
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chip_ver = 0;
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break;
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}
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return chip_ver;
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}
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uint32_t bootloader_common_get_chip_ver_pkg(void)
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{
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uint32_t pkg_version = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG);
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uint32_t pkg_version_4bit = REG_GET_FIELD(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_VER_PKG_4BIT);
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return (pkg_version_4bit << 3) | pkg_version;
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}
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int bootloader_clock_get_rated_freq_mhz()
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{
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//Check if ESP32 is rated for a CPU frequency of 160MHz only
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if (REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_RATED) &&
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REG_GET_BIT(EFUSE_BLK0_RDATA3_REG, EFUSE_RD_CHIP_CPU_FREQ_LOW)) {
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return 160;
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}
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return 240;
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}
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