kopia lustrzana https://github.com/espressif/esp-idf
90 wiersze
2.6 KiB
C
90 wiersze
2.6 KiB
C
/*
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* SPDX-FileCopyrightText: 2019-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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// The HAL layer for LEDC (common part)
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#include "esp_attr.h"
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#include "hal/ledc_hal.h"
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#include "soc/soc_caps.h"
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void ledc_hal_init(ledc_hal_context_t *hal, ledc_mode_t speed_mode)
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{
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//Get hardware instance.
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hal->dev = LEDC_LL_GET_HW();
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hal->speed_mode = speed_mode;
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}
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static inline ledc_clk_cfg_t ledc_hal_get_slow_clock_helper(ledc_hal_context_t *hal)
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{
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ledc_slow_clk_sel_t slow_clk = LEDC_SLOW_CLK_APB;
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ledc_hal_get_slow_clk_sel(hal, &slow_clk);
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switch (slow_clk) {
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case LEDC_SLOW_CLK_RTC8M:
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return LEDC_USE_RTC8M_CLK;
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#if SOC_LEDC_SUPPORT_XTAL_CLOCK
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case LEDC_SLOW_CLK_XTAL:
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return LEDC_USE_XTAL_CLK;
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#endif
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default:
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return LEDC_USE_APB_CLK;
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}
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}
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void ledc_hal_get_clk_cfg(ledc_hal_context_t *hal, ledc_timer_t timer_sel, ledc_clk_cfg_t *clk_cfg)
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{
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/* Use the following variable to retrieve the clock source used by the LEDC
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* hardware controler. */
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ledc_clk_src_t clk_src;
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/* Clock configuration to return to the driver. */
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ledc_clk_cfg_t driver_clk = LEDC_USE_APB_CLK;
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/* Get the timer-specific mux value. */
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ledc_hal_get_clock_source(hal, timer_sel, &clk_src);
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#if SOC_LEDC_SUPPORT_REF_TICK
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if (clk_src == LEDC_REF_TICK) {
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driver_clk = LEDC_USE_REF_TICK;
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} else
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#endif
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/* If the timer-specific mux is not set to REF_TICK, it either means that:
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* - The controler is in fast mode, and thus using APB clock (driver_clk
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* variable's default value)
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* - The controler is in slow mode and so, using a global clock,
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* so we have to retrieve that clock here.
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*/
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if (hal->speed_mode == LEDC_LOW_SPEED_MODE) {
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/* If the source clock used by LEDC hardware is not REF_TICKS, it is
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* necessary to retrieve the global clock source used. */
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driver_clk = ledc_hal_get_slow_clock_helper(hal);
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}
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*clk_cfg = driver_clk;
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}
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void ledc_hal_set_slow_clk(ledc_hal_context_t *hal, ledc_clk_cfg_t clk_cfg)
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{
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// For low speed channels, if RTC_8MCLK is used as the source clock, the `slow_clk_sel` register should be cleared, otherwise it should be set.
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ledc_slow_clk_sel_t slow_clk_sel;
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switch (clk_cfg) {
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case LEDC_USE_RTC8M_CLK:
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slow_clk_sel = LEDC_SLOW_CLK_RTC8M;
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break;
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#if SOC_LEDC_SUPPORT_XTAL_CLOCK
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case LEDC_USE_XTAL_CLK:
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slow_clk_sel = LEDC_SLOW_CLK_XTAL;
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break;
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#endif
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default:
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slow_clk_sel = LEDC_SLOW_CLK_APB;
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break;
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}
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ledc_hal_set_slow_clk_sel(hal, slow_clk_sel);
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}
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