kopia lustrzana https://github.com/espressif/esp-idf
239 wiersze
6.4 KiB
ArmAsm
239 wiersze
6.4 KiB
ArmAsm
// Copyright 2015-2017 Espressif Systems (Shanghai) PTE LTD
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#include "xtensa_rtos.h"
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#include "esp_private/panic_reason.h"
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#include "sdkconfig.h"
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#include "soc/soc.h"
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/*
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This file contains the default handlers for the high interrupt levels as well as some specialized exceptions.
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The default behaviour is to just exit the interrupt or call the panic handler on the exceptions
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*/
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#if XCHAL_HAVE_DEBUG
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.global xt_debugexception
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.weak xt_debugexception
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.set xt_debugexception, _xt_debugexception
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.section .iram1,"ax"
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.type _xt_debugexception,@function
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.align 4
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_xt_debugexception:
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#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
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#define XT_DEBUGCAUSE_DI (5)
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getcoreid a0
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#if (CONFIG_BTDM_CTRL_PINNED_TO_CORE == PRO_CPU_NUM)
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beqz a0, 1f
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#else
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bnez a0, 1f
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#endif
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rsr a0, DEBUGCAUSE
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extui a0, a0, XT_DEBUGCAUSE_DI, 1
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bnez a0, _xt_debug_di_exc
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1:
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#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
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movi a0,PANIC_RSN_DEBUGEXCEPTION
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wsr a0,EXCCAUSE
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/* _xt_panic assumes a level 1 exception. As we're
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crashing anyhow, copy EPC & EXCSAVE from DEBUGLEVEL
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to level 1. */
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rsr a0,(EPC + XCHAL_DEBUGLEVEL)
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wsr a0,EPC_1
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rsr a0,(EXCSAVE + XCHAL_DEBUGLEVEL)
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wsr a0,EXCSAVE_1
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call0 _xt_panic /* does not return */
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rfi XCHAL_DEBUGLEVEL
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#if (CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
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.align 4
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_xt_debug_di_exc:
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/*
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The delay time can be calculated by the following formula:
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T = ceil(0.25 + max(t1, t2)) us
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t1 = 80 / f1, t2 = (1 + 14/N) * 20 / f2
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f1: PSRAM access frequency, unit: MHz.
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f2: Flash access frequency, unit: MHz.
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When flash is slow/fast read, N = 1.
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When flash is DOUT/DIO read, N = 2.
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When flash is QOUT/QIO read, N = 4.
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And after testing, when CPU frequency is 240 MHz, it will take 1us to loop 27 times.
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*/
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#if defined(CONFIG_ESPTOOLPY_FLASHMODE_QIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_QOUT)
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# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
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movi a0, 54
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# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
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movi a0, 81
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# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
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movi a0, 81
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# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
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movi a0, 108
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# else
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movi a0, 135
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# endif
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#elif defined(CONFIG_ESPTOOLPY_FLASHMODE_DIO) || defined(CONFIG_ESPTOOLPY_FLASHMODE_DOUT)
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# if defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_80M)
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movi a0, 81
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# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_80M) && defined(CONFIG_SPIRAM_SPEED_40M)
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movi a0, 81
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# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_40M) && defined(CONFIG_SPIRAM_SPEED_40M)
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movi a0, 135
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# elif defined(CONFIG_ESPTOOLPY_FLASHFREQ_26M) && defined(CONFIG_SPIRAM_SPEED_40M)
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movi a0, 189
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# else
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movi a0, 243
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# endif
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#else
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movi a0, 243
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#endif
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1: addi a0, a0, -1 /* delay_us(N) */
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.rept 4
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nop
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.endr
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bnez a0, 1b
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rsr a0, EXCSAVE+XCHAL_DEBUGLEVEL
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rfi XCHAL_DEBUGLEVEL
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#endif //(CONFIG_ESP32_ECO3_CACHE_LOCK_FIX && CONFIG_BTDM_CTRL_HLI)
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#endif /* Debug exception */
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#if XCHAL_NUM_INTLEVELS >=2 && XCHAL_EXCM_LEVEL <2 && XCHAL_DEBUGLEVEL !=2
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.global xt_highint2
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.weak xt_highint2
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.set xt_highint2, _xt_highint2
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.section .iram1,"ax"
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.type _xt_highint2,@function
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.align 4
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_xt_highint2:
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/* Default handler does nothing; just returns */
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.align 4
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.L_xt_highint2_exit:
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rsr a0, EXCSAVE_2 /* restore a0 */
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rfi 2
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#endif /* Level 2 */
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#if XCHAL_NUM_INTLEVELS >=3 && XCHAL_EXCM_LEVEL <3 && XCHAL_DEBUGLEVEL !=3
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.global xt_highint3
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.weak xt_highint3
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.set xt_highint3, _xt_highint3
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.section .iram1,"ax"
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.type _xt_highint3,@function
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.align 4
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_xt_highint3:
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/* Default handler does nothing; just returns */
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.align 4
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.L_xt_highint3_exit:
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rsr a0, EXCSAVE_3 /* restore a0 */
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rfi 3
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#endif /* Level 3 */
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#if XCHAL_NUM_INTLEVELS >=4 && XCHAL_EXCM_LEVEL <4 && XCHAL_DEBUGLEVEL !=4
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.global xt_highint4
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.weak xt_highint4
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.set xt_highint4, _xt_highint4
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.section .iram1,"ax"
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.type _xt_highint4,@function
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.align 4
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_xt_highint4:
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/* Default handler does nothing; just returns */
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.align 4
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.L_xt_highint4_exit:
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rsr a0, EXCSAVE_4 /* restore a0 */
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rfi 4
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#endif /* Level 4 */
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#if XCHAL_NUM_INTLEVELS >=5 && XCHAL_EXCM_LEVEL <5 && XCHAL_DEBUGLEVEL !=5
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.global xt_highint5
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.weak xt_highint5
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.set xt_highint5, _xt_highint5
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.section .iram1,"ax"
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.type _xt_highint5,@function
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.align 4
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_xt_highint5:
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/* Default handler does nothing; just returns */
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.align 4
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.L_xt_highint5_exit:
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rsr a0, EXCSAVE_5 /* restore a0 */
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rfi 5
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#endif /* Level 5 */
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#if XCHAL_NUM_INTLEVELS >=6 && XCHAL_EXCM_LEVEL <6 && XCHAL_DEBUGLEVEL !=6
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.global _xt_highint6
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.global xt_highint6
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.weak xt_highint6
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.set xt_highint6, _xt_highint6
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.section .iram1,"ax"
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.type _xt_highint6,@function
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.align 4
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_xt_highint6:
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/* Default handler does nothing; just returns */
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.align 4
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.L_xt_highint6_exit:
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rsr a0, EXCSAVE_6 /* restore a0 */
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rfi 6
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#endif /* Level 6 */
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#if XCHAL_HAVE_NMI
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.global _xt_nmi
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.global xt_nmi
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.weak xt_nmi
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.set xt_nmi, _xt_nmi
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.section .iram1,"ax"
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.type _xt_nmi,@function
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.align 4
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_xt_nmi:
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/* Default handler does nothing; just returns */
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.align 4
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.L_xt_nmi_exit:
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rsr a0, EXCSAVE + XCHAL_NMILEVEL /* restore a0 */
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rfi XCHAL_NMILEVEL
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#endif /* NMI */
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