kopia lustrzana https://github.com/espressif/esp-idf
944 wiersze
33 KiB
C
944 wiersze
33 KiB
C
/*
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* SPDX-FileCopyrightText: 2016-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <esp_types.h>
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#include <stdlib.h>
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#include <ctype.h>
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#include <string.h>
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#include "sdkconfig.h"
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#include "esp_intr_alloc.h"
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#include "esp_log.h"
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#include "esp_pm.h"
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#include "esp_check.h"
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#include "sys/lock.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "freertos/timers.h"
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#include "freertos/ringbuf.h"
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#include "esp_private/periph_ctrl.h"
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#include "driver/gpio.h"
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#include "driver/adc.h"
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#include "hal/adc_types.h"
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#include "hal/adc_hal.h"
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#include "hal/dma_types.h"
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//For calibration
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#if CONFIG_IDF_TARGET_ESP32S2
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#include "esp_efuse_rtc_table.h"
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#elif SOC_ADC_CALIBRATION_V1_SUPPORTED
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#include "esp_efuse_rtc_calib.h"
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#endif
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//For DMA
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#if SOC_GDMA_SUPPORTED
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#include "esp_private/gdma.h"
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#elif CONFIG_IDF_TARGET_ESP32S2
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#include "hal/spi_types.h"
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#include "driver/spi_common_internal.h"
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#elif CONFIG_IDF_TARGET_ESP32
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#include "driver/i2s.h"
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#include "hal/i2s_types.h"
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#include "soc/i2s_periph.h"
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#include "esp_private/i2s_platform.h"
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#endif
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static const char *ADC_TAG = "ADC";
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#define ADC_GET_IO_NUM(periph, channel) (adc_channel_io_map[periph][channel])
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extern portMUX_TYPE rtc_spinlock; //TODO: Will be placed in the appropriate position after the rtc module is finished.
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#define ADC_ENTER_CRITICAL() portENTER_CRITICAL(&rtc_spinlock)
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#define ADC_EXIT_CRITICAL() portEXIT_CRITICAL(&rtc_spinlock)
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/**
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* 1. sar_adc1_lock: this mutex lock is to protect the SARADC1 module.
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* 2. sar_adc2_lock: this mutex lock is to protect the SARADC2 module.
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* 3. adc_reg_lock: this spin lock is to protect the shared registers used by ADC1 / ADC2 single read mode.
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*/
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static _lock_t sar_adc1_lock;
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#define SAR_ADC1_LOCK_ACQUIRE() _lock_acquire(&sar_adc1_lock)
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#define SAR_ADC1_LOCK_RELEASE() _lock_release(&sar_adc1_lock)
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static _lock_t sar_adc2_lock;
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#define SAR_ADC2_LOCK_ACQUIRE() _lock_acquire(&sar_adc2_lock)
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#define SAR_ADC2_LOCK_RELEASE() _lock_release(&sar_adc2_lock)
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portMUX_TYPE adc_reg_lock = portMUX_INITIALIZER_UNLOCKED;
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#define ADC_REG_LOCK_ENTER() portENTER_CRITICAL(&adc_reg_lock)
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#define ADC_REG_LOCK_EXIT() portEXIT_CRITICAL(&adc_reg_lock)
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#define INTERNAL_BUF_NUM 5
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/*---------------------------------------------------------------
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Digital Controller Context
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---------------------------------------------------------------*/
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typedef struct adc_digi_context_t {
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uint8_t *rx_dma_buf; //dma buffer
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adc_hal_context_t hal; //hal context
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#if SOC_GDMA_SUPPORTED
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gdma_channel_handle_t rx_dma_channel; //dma rx channel handle
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#elif CONFIG_IDF_TARGET_ESP32S2
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spi_host_device_t spi_host; //ADC uses this SPI DMA
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intr_handle_t intr_hdl; //Interrupt handler
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#elif CONFIG_IDF_TARGET_ESP32
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i2s_port_t i2s_host; //ADC uses this I2S DMA
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intr_handle_t intr_hdl; //Interrupt handler
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#endif
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RingbufHandle_t ringbuf_hdl; //RX ringbuffer handler
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intptr_t rx_eof_desc_addr; //eof descriptor address of RX channel
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bool ringbuf_overflow_flag; //1: ringbuffer overflow
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bool driver_start_flag; //1: driver is started; 0: driver is stoped
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bool use_adc1; //1: ADC unit1 will be used; 0: ADC unit1 won't be used.
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bool use_adc2; //1: ADC unit2 will be used; 0: ADC unit2 won't be used. This determines whether to acquire sar_adc2_mutex lock or not.
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adc_atten_t adc1_atten; //Attenuation for ADC1. On this chip each ADC can only support one attenuation.
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adc_atten_t adc2_atten; //Attenuation for ADC2. On this chip each ADC can only support one attenuation.
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adc_hal_digi_ctrlr_cfg_t hal_digi_ctrlr_cfg; //Hal digital controller configuration
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esp_pm_lock_handle_t pm_lock; //For power management
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} adc_digi_context_t;
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static adc_digi_context_t *s_adc_digi_ctx = NULL;
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#ifdef CONFIG_PM_ENABLE
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//Only for deprecated API
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extern esp_pm_lock_handle_t adc_digi_arbiter_lock;
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#endif //CONFIG_PM_ENABLE
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#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t chan, adc_atten_t atten);
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#endif
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/*---------------------------------------------------------------
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ADC Continuous Read Mode (via DMA)
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---------------------------------------------------------------*/
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//Function to address transaction
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static IRAM_ATTR bool s_adc_dma_intr(adc_digi_context_t *adc_digi_ctx);
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#if SOC_GDMA_SUPPORTED
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static IRAM_ATTR bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data);
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#else
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static IRAM_ATTR void adc_dma_intr_handler(void *arg);
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#endif
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static int8_t adc_digi_get_io_num(uint8_t adc_unit, uint8_t adc_channel)
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{
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return adc_channel_io_map[adc_unit][adc_channel];
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}
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static esp_err_t adc_digi_gpio_init(adc_unit_t adc_unit, uint16_t channel_mask)
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{
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esp_err_t ret = ESP_OK;
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uint64_t gpio_mask = 0;
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uint32_t n = 0;
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int8_t io = 0;
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while (channel_mask) {
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if (channel_mask & 0x1) {
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io = adc_digi_get_io_num(adc_unit, n);
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if (io < 0) {
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return ESP_ERR_INVALID_ARG;
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}
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gpio_mask |= BIT64(io);
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}
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channel_mask = channel_mask >> 1;
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n++;
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}
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gpio_config_t cfg = {
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.pin_bit_mask = gpio_mask,
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.mode = GPIO_MODE_DISABLE,
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};
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ret = gpio_config(&cfg);
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return ret;
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}
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esp_err_t adc_digi_initialize(const adc_digi_init_config_t *init_config)
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{
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esp_err_t ret = ESP_OK;
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s_adc_digi_ctx = calloc(1, sizeof(adc_digi_context_t));
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if (s_adc_digi_ctx == NULL) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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//ringbuffer
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s_adc_digi_ctx->ringbuf_hdl = xRingbufferCreate(init_config->max_store_buf_size, RINGBUF_TYPE_BYTEBUF);
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if (!s_adc_digi_ctx->ringbuf_hdl) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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//malloc internal buffer used by DMA
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s_adc_digi_ctx->rx_dma_buf = heap_caps_calloc(1, init_config->conv_num_each_intr * INTERNAL_BUF_NUM, MALLOC_CAP_INTERNAL | MALLOC_CAP_DMA);
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if (!s_adc_digi_ctx->rx_dma_buf) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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//malloc dma descriptor
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s_adc_digi_ctx->hal.rx_desc = heap_caps_calloc(1, (sizeof(dma_descriptor_t)) * INTERNAL_BUF_NUM, MALLOC_CAP_DMA);
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if (!s_adc_digi_ctx->hal.rx_desc) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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//malloc pattern table
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s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern = calloc(1, SOC_ADC_PATT_LEN_MAX * sizeof(adc_digi_pattern_config_t));
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if (!s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern) {
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ret = ESP_ERR_NO_MEM;
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goto cleanup;
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}
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#if CONFIG_PM_ENABLE
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ret = esp_pm_lock_create(ESP_PM_APB_FREQ_MAX, 0, "adc_dma", &s_adc_digi_ctx->pm_lock);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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#endif //CONFIG_PM_ENABLE
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//init gpio pins
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if (init_config->adc1_chan_mask) {
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ret = adc_digi_gpio_init(ADC_NUM_1, init_config->adc1_chan_mask);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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}
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if (init_config->adc2_chan_mask) {
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ret = adc_digi_gpio_init(ADC_NUM_2, init_config->adc2_chan_mask);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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}
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#if SOC_GDMA_SUPPORTED
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//alloc rx gdma channel
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gdma_channel_alloc_config_t rx_alloc_config = {
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.direction = GDMA_CHANNEL_DIRECTION_RX,
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};
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ret = gdma_new_channel(&rx_alloc_config, &s_adc_digi_ctx->rx_dma_channel);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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gdma_connect(s_adc_digi_ctx->rx_dma_channel, GDMA_MAKE_TRIGGER(GDMA_TRIG_PERIPH_ADC, 0));
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gdma_strategy_config_t strategy_config = {
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.auto_update_desc = true,
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.owner_check = true
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};
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gdma_apply_strategy(s_adc_digi_ctx->rx_dma_channel, &strategy_config);
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gdma_rx_event_callbacks_t cbs = {
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.on_recv_eof = adc_dma_in_suc_eof_callback
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};
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gdma_register_rx_event_callbacks(s_adc_digi_ctx->rx_dma_channel, &cbs, s_adc_digi_ctx);
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int dma_chan;
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gdma_get_channel_id(s_adc_digi_ctx->rx_dma_channel, &dma_chan);
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#elif CONFIG_IDF_TARGET_ESP32S2
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//ADC utilises SPI3 DMA on ESP32S2
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bool spi_success = false;
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uint32_t dma_chan = 0;
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spi_success = spicommon_periph_claim(SPI3_HOST, "adc");
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ret = spicommon_dma_chan_alloc(SPI3_HOST, SPI_DMA_CH_AUTO, &dma_chan, &dma_chan);
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if (ret == ESP_OK) {
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s_adc_digi_ctx->spi_host = SPI3_HOST;
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}
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if (!spi_success || (s_adc_digi_ctx->spi_host != SPI3_HOST)) {
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goto cleanup;
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}
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ret = esp_intr_alloc(spicommon_irqdma_source_for_host(s_adc_digi_ctx->spi_host), 0, adc_dma_intr_handler,
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(void *)s_adc_digi_ctx, &s_adc_digi_ctx->intr_hdl);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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#elif CONFIG_IDF_TARGET_ESP32
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//ADC utilises I2S0 DMA on ESP32
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uint32_t dma_chan = 0;
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ret = i2s_priv_register_object(&s_adc_digi_ctx, I2S_NUM_0);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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s_adc_digi_ctx->i2s_host = I2S_NUM_0;
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ret = esp_intr_alloc(i2s_periph_signal[s_adc_digi_ctx->i2s_host].irq, 0, adc_dma_intr_handler,
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(void *)s_adc_digi_ctx, &s_adc_digi_ctx->intr_hdl);
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if (ret != ESP_OK) {
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goto cleanup;
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}
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#endif
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adc_hal_config_t config = {
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#if SOC_GDMA_SUPPORTED
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.dev = (void *)GDMA_LL_GET_HW(0),
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#elif CONFIG_IDF_TARGET_ESP32S2
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.dev = (void *)SPI_LL_GET_HW(s_adc_digi_ctx->spi_host),
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#elif CONFIG_IDF_TARGET_ESP32
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.dev = (void *)I2S_LL_GET_HW(s_adc_digi_ctx->i2s_host),
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#endif
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.desc_max_num = INTERNAL_BUF_NUM,
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.dma_chan = dma_chan,
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.eof_num = init_config->conv_num_each_intr / ADC_HAL_DATA_LEN_PER_CONV
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};
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adc_hal_context_config(&s_adc_digi_ctx->hal, &config);
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//enable ADC digital part
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periph_module_enable(PERIPH_SARADC_MODULE);
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//reset ADC digital part
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periph_module_reset(PERIPH_SARADC_MODULE);
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#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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adc_hal_calibration_init(ADC_NUM_1);
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adc_hal_calibration_init(ADC_NUM_2);
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#endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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return ret;
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cleanup:
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adc_digi_deinitialize();
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return ret;
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}
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#if SOC_GDMA_SUPPORTED
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static IRAM_ATTR bool adc_dma_in_suc_eof_callback(gdma_channel_handle_t dma_chan, gdma_event_data_t *event_data, void *user_data)
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{
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assert(event_data);
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s_adc_digi_ctx->rx_eof_desc_addr = event_data->rx_eof_desc_addr;
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return s_adc_dma_intr(user_data);
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}
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#else
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static IRAM_ATTR void adc_dma_intr_handler(void *arg)
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{
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adc_digi_context_t *ctx = (adc_digi_context_t *)arg;
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bool need_yield = false;
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bool conversion_finish = adc_hal_check_event(&ctx->hal, ADC_HAL_DMA_INTR_MASK);
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if (conversion_finish) {
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adc_hal_digi_clr_intr(&s_adc_digi_ctx->hal, ADC_HAL_DMA_INTR_MASK);
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intptr_t desc_addr = adc_hal_get_desc_addr(&ctx->hal);
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ctx->rx_eof_desc_addr = desc_addr;
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need_yield = s_adc_dma_intr(ctx);
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}
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if (need_yield) {
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portYIELD_FROM_ISR();
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}
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}
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#endif
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static IRAM_ATTR bool s_adc_dma_intr(adc_digi_context_t *adc_digi_ctx)
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{
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portBASE_TYPE taskAwoken = 0;
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BaseType_t ret;
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adc_hal_dma_desc_status_t status = false;
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dma_descriptor_t *current_desc = NULL;
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while (1) {
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status = adc_hal_get_reading_result(&adc_digi_ctx->hal, adc_digi_ctx->rx_eof_desc_addr, ¤t_desc);
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if (status != ADC_HAL_DMA_DESC_VALID) {
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break;
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}
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ret = xRingbufferSendFromISR(adc_digi_ctx->ringbuf_hdl, current_desc->buffer, current_desc->dw0.length, &taskAwoken);
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if (ret == pdFALSE) {
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//ringbuffer overflow
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adc_digi_ctx->ringbuf_overflow_flag = 1;
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}
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}
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if (status == ADC_HAL_DMA_DESC_NULL) {
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//start next turns of dma operation
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adc_hal_digi_start(&adc_digi_ctx->hal, adc_digi_ctx->rx_dma_buf);
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}
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return (taskAwoken == pdTRUE);
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}
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esp_err_t adc_digi_start(void)
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{
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if (s_adc_digi_ctx) {
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if (s_adc_digi_ctx->driver_start_flag != 0) {
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ESP_LOGE(ADC_TAG, "The driver is already started");
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return ESP_ERR_INVALID_STATE;
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}
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adc_power_acquire();
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//reset flags
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s_adc_digi_ctx->ringbuf_overflow_flag = 0;
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s_adc_digi_ctx->driver_start_flag = 1;
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if (s_adc_digi_ctx->use_adc1) {
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SAR_ADC1_LOCK_ACQUIRE();
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}
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if (s_adc_digi_ctx->use_adc2) {
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SAR_ADC2_LOCK_ACQUIRE();
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}
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#if CONFIG_PM_ENABLE
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// Lock APB frequency while ADC driver is in use
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esp_pm_lock_acquire(s_adc_digi_ctx->pm_lock);
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#endif
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#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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if (s_adc_digi_ctx->use_adc1) {
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uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_1, ADC_CHANNEL_MAX, s_adc_digi_ctx->adc1_atten);
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adc_hal_set_calibration_param(ADC_NUM_1, cal_val);
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}
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if (s_adc_digi_ctx->use_adc2) {
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uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_2, ADC_CHANNEL_MAX, s_adc_digi_ctx->adc2_atten);
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adc_hal_set_calibration_param(ADC_NUM_2, cal_val);
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}
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#endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
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adc_hal_init();
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#if SOC_ADC_ARBITER_SUPPORTED
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adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
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adc_hal_arbiter_config(&config);
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#endif //#if SOC_ADC_ARBITER_SUPPORTED
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adc_hal_set_controller(ADC_NUM_1, ADC_HAL_CONTINUOUS_READ_MODE);
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adc_hal_set_controller(ADC_NUM_2, ADC_HAL_CONTINUOUS_READ_MODE);
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adc_hal_digi_init(&s_adc_digi_ctx->hal);
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adc_hal_digi_controller_config(&s_adc_digi_ctx->hal, &s_adc_digi_ctx->hal_digi_ctrlr_cfg);
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//start conversion
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adc_hal_digi_start(&s_adc_digi_ctx->hal, s_adc_digi_ctx->rx_dma_buf);
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}
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#if CONFIG_IDF_TARGET_ESP32S2
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//For being compatible with the deprecated behaviour
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else {
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ESP_LOGE(ADC_TAG, "API used without driver initialization before. The following behaviour is deprecated!!");
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#ifdef CONFIG_PM_ENABLE
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ESP_RETURN_ON_FALSE((adc_digi_arbiter_lock), ESP_FAIL, ADC_TAG, "Should start after call `adc_digi_controller_config`");
|
|
esp_pm_lock_acquire(adc_digi_arbiter_lock);
|
|
#endif
|
|
ADC_ENTER_CRITICAL();
|
|
adc_ll_digi_dma_enable();
|
|
adc_ll_digi_trigger_enable();
|
|
ADC_EXIT_CRITICAL();
|
|
}
|
|
#endif //#if CONFIG_IDF_TARGET_ESP32S2
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t adc_digi_stop(void)
|
|
{
|
|
if (s_adc_digi_ctx) {
|
|
if (s_adc_digi_ctx->driver_start_flag != 1) {
|
|
ESP_LOGE(ADC_TAG, "The driver is already stopped");
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
s_adc_digi_ctx->driver_start_flag = 0;
|
|
|
|
//disable the in suc eof intrrupt
|
|
adc_hal_digi_dis_intr(&s_adc_digi_ctx->hal, ADC_HAL_DMA_INTR_MASK);
|
|
//clear the in suc eof interrupt
|
|
adc_hal_digi_clr_intr(&s_adc_digi_ctx->hal, ADC_HAL_DMA_INTR_MASK);
|
|
//stop ADC
|
|
adc_hal_digi_stop(&s_adc_digi_ctx->hal);
|
|
|
|
adc_hal_digi_deinit(&s_adc_digi_ctx->hal);
|
|
#if CONFIG_PM_ENABLE
|
|
if (s_adc_digi_ctx->pm_lock) {
|
|
esp_pm_lock_release(s_adc_digi_ctx->pm_lock);
|
|
}
|
|
#endif //CONFIG_PM_ENABLE
|
|
|
|
if (s_adc_digi_ctx->use_adc1) {
|
|
SAR_ADC1_LOCK_RELEASE();
|
|
}
|
|
if (s_adc_digi_ctx->use_adc2) {
|
|
SAR_ADC2_LOCK_RELEASE();
|
|
}
|
|
adc_power_release();
|
|
}
|
|
#if CONFIG_IDF_TARGET_ESP32S2
|
|
else {
|
|
//For being compatible with the deprecated behaviour
|
|
ESP_LOGE(ADC_TAG, "API used without driver initialization before. The following behaviour is deprecated!!");
|
|
#ifdef CONFIG_PM_ENABLE
|
|
if (adc_digi_arbiter_lock) {
|
|
esp_pm_lock_release(adc_digi_arbiter_lock);
|
|
}
|
|
#endif
|
|
ADC_ENTER_CRITICAL();
|
|
adc_ll_digi_trigger_disable();
|
|
adc_ll_digi_dma_disable();
|
|
ADC_EXIT_CRITICAL();
|
|
}
|
|
#endif //#if CONFIG_IDF_TARGET_ESP32S2
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t adc_digi_read_bytes(uint8_t *buf, uint32_t length_max, uint32_t *out_length, uint32_t timeout_ms)
|
|
{
|
|
TickType_t ticks_to_wait;
|
|
esp_err_t ret = ESP_OK;
|
|
uint8_t *data = NULL;
|
|
size_t size = 0;
|
|
|
|
ticks_to_wait = timeout_ms / portTICK_PERIOD_MS;
|
|
if (timeout_ms == ADC_MAX_DELAY) {
|
|
ticks_to_wait = portMAX_DELAY;
|
|
}
|
|
|
|
data = xRingbufferReceiveUpTo(s_adc_digi_ctx->ringbuf_hdl, &size, ticks_to_wait, length_max);
|
|
if (!data) {
|
|
ESP_LOGV(ADC_TAG, "No data, increase timeout or reduce conv_num_each_intr");
|
|
ret = ESP_ERR_TIMEOUT;
|
|
*out_length = 0;
|
|
return ret;
|
|
}
|
|
|
|
memcpy(buf, data, size);
|
|
vRingbufferReturnItem(s_adc_digi_ctx->ringbuf_hdl, data);
|
|
assert((size % 4) == 0);
|
|
*out_length = size;
|
|
|
|
if (s_adc_digi_ctx->ringbuf_overflow_flag) {
|
|
ret = ESP_ERR_INVALID_STATE;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
esp_err_t adc_digi_deinitialize(void)
|
|
{
|
|
if (!s_adc_digi_ctx) {
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
|
|
if (s_adc_digi_ctx->driver_start_flag != 0) {
|
|
ESP_LOGE(ADC_TAG, "The driver is not stopped");
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
|
|
if (s_adc_digi_ctx->ringbuf_hdl) {
|
|
vRingbufferDelete(s_adc_digi_ctx->ringbuf_hdl);
|
|
s_adc_digi_ctx->ringbuf_hdl = NULL;
|
|
}
|
|
|
|
#if CONFIG_PM_ENABLE
|
|
if (s_adc_digi_ctx->pm_lock) {
|
|
esp_pm_lock_delete(s_adc_digi_ctx->pm_lock);
|
|
}
|
|
#endif //CONFIG_PM_ENABLE
|
|
|
|
free(s_adc_digi_ctx->rx_dma_buf);
|
|
free(s_adc_digi_ctx->hal.rx_desc);
|
|
free(s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern);
|
|
#if SOC_GDMA_SUPPORTED
|
|
gdma_disconnect(s_adc_digi_ctx->rx_dma_channel);
|
|
gdma_del_channel(s_adc_digi_ctx->rx_dma_channel);
|
|
#elif CONFIG_IDF_TARGET_ESP32S2
|
|
esp_intr_free(s_adc_digi_ctx->intr_hdl);
|
|
spicommon_dma_chan_free(s_adc_digi_ctx->spi_host);
|
|
spicommon_periph_free(s_adc_digi_ctx->spi_host);
|
|
#elif CONFIG_IDF_TARGET_ESP32
|
|
esp_intr_free(s_adc_digi_ctx->intr_hdl);
|
|
i2s_priv_deregister_object(s_adc_digi_ctx->i2s_host);
|
|
#endif
|
|
free(s_adc_digi_ctx);
|
|
s_adc_digi_ctx = NULL;
|
|
|
|
periph_module_disable(PERIPH_SARADC_MODULE);
|
|
|
|
return ESP_OK;
|
|
}
|
|
|
|
/*---------------------------------------------------------------
|
|
Digital controller setting
|
|
---------------------------------------------------------------*/
|
|
esp_err_t adc_digi_controller_configure(const adc_digi_configuration_t *config)
|
|
{
|
|
if (!s_adc_digi_ctx) {
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
|
|
//Pattern related check
|
|
ESP_RETURN_ON_FALSE(config->pattern_num <= SOC_ADC_PATT_LEN_MAX, ESP_ERR_INVALID_ARG, ADC_TAG, "Max pattern num is %d", SOC_ADC_PATT_LEN_MAX);
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
for (int i = 0; i < config->pattern_num; i++) {
|
|
ESP_RETURN_ON_FALSE((config->adc_pattern[i].bit_width >= SOC_ADC_DIGI_MIN_BITWIDTH && config->adc_pattern->bit_width <= SOC_ADC_DIGI_MAX_BITWIDTH), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC bitwidth not supported");
|
|
ESP_RETURN_ON_FALSE(config->adc_pattern[i].unit == 0, ESP_ERR_INVALID_ARG, ADC_TAG, "Only support using ADC1 DMA mode");
|
|
}
|
|
#else
|
|
for (int i = 0; i < config->pattern_num; i++) {
|
|
ESP_RETURN_ON_FALSE((config->adc_pattern[i].bit_width == SOC_ADC_DIGI_MAX_BITWIDTH), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC bitwidth not supported");
|
|
}
|
|
#endif
|
|
ESP_RETURN_ON_FALSE(config->sample_freq_hz <= SOC_ADC_SAMPLE_FREQ_THRES_HIGH && config->sample_freq_hz >= SOC_ADC_SAMPLE_FREQ_THRES_LOW, ESP_ERR_INVALID_ARG, ADC_TAG, "ADC sampling frequency out of range");
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
ESP_RETURN_ON_FALSE(config->conv_limit_en == 1, ESP_ERR_INVALID_ARG, ADC_TAG, "`conv_limit_en` should be set to 1");
|
|
#endif
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32
|
|
ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE1, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type1");
|
|
#elif CONFIG_IDF_TARGET_ESP32S2
|
|
if (config->conv_mode == ADC_CONV_BOTH_UNIT || config->conv_mode == ADC_CONV_ALTER_UNIT) {
|
|
ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE2, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type2");
|
|
} else if (config->conv_mode == ADC_CONV_SINGLE_UNIT_1 || config->conv_mode == ADC_CONV_SINGLE_UNIT_2) {
|
|
ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE1, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type1");
|
|
}
|
|
#else
|
|
ESP_RETURN_ON_FALSE(config->format == ADC_DIGI_OUTPUT_FORMAT_TYPE2, ESP_ERR_INVALID_ARG, ADC_TAG, "Please use type2");
|
|
#endif
|
|
|
|
s_adc_digi_ctx->hal_digi_ctrlr_cfg.conv_limit_en = config->conv_limit_en;
|
|
s_adc_digi_ctx->hal_digi_ctrlr_cfg.conv_limit_num = config->conv_limit_num;
|
|
s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern_len = config->pattern_num;
|
|
s_adc_digi_ctx->hal_digi_ctrlr_cfg.sample_freq_hz = config->sample_freq_hz;
|
|
s_adc_digi_ctx->hal_digi_ctrlr_cfg.conv_mode = config->conv_mode;
|
|
memcpy(s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern, config->adc_pattern, config->pattern_num * sizeof(adc_digi_pattern_config_t));
|
|
|
|
const int atten_uninitialized = 999;
|
|
s_adc_digi_ctx->adc1_atten = atten_uninitialized;
|
|
s_adc_digi_ctx->adc2_atten = atten_uninitialized;
|
|
s_adc_digi_ctx->use_adc1 = 0;
|
|
s_adc_digi_ctx->use_adc2 = 0;
|
|
for (int i = 0; i < config->pattern_num; i++) {
|
|
const adc_digi_pattern_config_t *pat = &config->adc_pattern[i];
|
|
if (pat->unit == ADC_NUM_1) {
|
|
s_adc_digi_ctx->use_adc1 = 1;
|
|
|
|
if (s_adc_digi_ctx->adc1_atten == atten_uninitialized) {
|
|
s_adc_digi_ctx->adc1_atten = pat->atten;
|
|
} else if (s_adc_digi_ctx->adc1_atten != pat->atten) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
} else if (pat->unit == ADC_NUM_2) {
|
|
//See whether ADC2 will be used or not. If yes, the ``sar_adc2_mutex`` should be acquired in the continuous read driver
|
|
s_adc_digi_ctx->use_adc2 = 1;
|
|
|
|
if (s_adc_digi_ctx->adc2_atten == atten_uninitialized) {
|
|
s_adc_digi_ctx->adc2_atten = pat->atten;
|
|
} else if (s_adc_digi_ctx->adc2_atten != pat->atten) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
}
|
|
}
|
|
|
|
return ESP_OK;
|
|
}
|
|
|
|
|
|
#if CONFIG_IDF_TARGET_ESP32C3
|
|
/*---------------------------------------------------------------
|
|
ADC Single Read Mode
|
|
---------------------------------------------------------------*/
|
|
static adc_atten_t s_atten1_single[ADC1_CHANNEL_MAX]; //Array saving attenuate of each channel of ADC1, used by single read API
|
|
static adc_atten_t s_atten2_single[ADC2_CHANNEL_MAX]; //Array saving attenuate of each channel of ADC2, used by single read API
|
|
|
|
esp_err_t adc_vref_to_gpio(adc_unit_t adc_unit, gpio_num_t gpio)
|
|
{
|
|
esp_err_t ret;
|
|
uint32_t channel = ADC2_CHANNEL_MAX;
|
|
if (adc_unit == ADC_UNIT_2) {
|
|
for (int i = 0; i < ADC2_CHANNEL_MAX; i++) {
|
|
if (gpio == ADC_GET_IO_NUM(ADC_NUM_2, i)) {
|
|
channel = i;
|
|
break;
|
|
}
|
|
}
|
|
if (channel == ADC2_CHANNEL_MAX) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
}
|
|
|
|
adc_power_acquire();
|
|
if (adc_unit & ADC_UNIT_1) {
|
|
ADC_ENTER_CRITICAL();
|
|
adc_hal_vref_output(ADC_NUM_1, channel, true);
|
|
ADC_EXIT_CRITICAL();
|
|
} else if (adc_unit & ADC_UNIT_2) {
|
|
ADC_ENTER_CRITICAL();
|
|
adc_hal_vref_output(ADC_NUM_2, channel, true);
|
|
ADC_EXIT_CRITICAL();
|
|
}
|
|
|
|
ret = adc_digi_gpio_init(ADC_NUM_2, BIT(channel));
|
|
|
|
return ret;
|
|
}
|
|
|
|
esp_err_t adc1_config_width(adc_bits_width_t width_bit)
|
|
{
|
|
//On ESP32C3, the data width is always 12-bits.
|
|
if (width_bit != ADC_WIDTH_BIT_12) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t adc1_config_channel_atten(adc1_channel_t channel, adc_atten_t atten)
|
|
{
|
|
ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_NUM_1), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC1 channel error");
|
|
ESP_RETURN_ON_FALSE((atten < ADC_ATTEN_MAX), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC Atten Err");
|
|
|
|
esp_err_t ret = ESP_OK;
|
|
s_atten1_single[channel] = atten;
|
|
ret = adc_digi_gpio_init(ADC_NUM_1, BIT(channel));
|
|
|
|
adc_hal_calibration_init(ADC_NUM_1);
|
|
|
|
return ret;
|
|
}
|
|
|
|
int adc1_get_raw(adc1_channel_t channel)
|
|
{
|
|
int raw_out = 0;
|
|
|
|
periph_module_enable(PERIPH_SARADC_MODULE);
|
|
adc_power_acquire();
|
|
|
|
SAR_ADC1_LOCK_ACQUIRE();
|
|
|
|
adc_atten_t atten = s_atten1_single[channel];
|
|
uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_1, channel, atten);
|
|
adc_hal_set_calibration_param(ADC_NUM_1, cal_val);
|
|
|
|
ADC_REG_LOCK_ENTER();
|
|
adc_hal_set_atten(ADC_NUM_2, channel, atten);
|
|
adc_hal_convert(ADC_NUM_1, channel, &raw_out);
|
|
ADC_REG_LOCK_EXIT();
|
|
|
|
SAR_ADC1_LOCK_RELEASE();
|
|
|
|
adc_power_release();
|
|
periph_module_disable(PERIPH_SARADC_MODULE);
|
|
|
|
return raw_out;
|
|
}
|
|
|
|
esp_err_t adc2_config_channel_atten(adc2_channel_t channel, adc_atten_t atten)
|
|
{
|
|
ESP_RETURN_ON_FALSE(channel < SOC_ADC_CHANNEL_NUM(ADC_NUM_2), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC2 channel error");
|
|
ESP_RETURN_ON_FALSE((atten <= ADC_ATTEN_11db), ESP_ERR_INVALID_ARG, ADC_TAG, "ADC2 Atten Err");
|
|
|
|
esp_err_t ret = ESP_OK;
|
|
s_atten2_single[channel] = atten;
|
|
ret = adc_digi_gpio_init(ADC_NUM_2, BIT(channel));
|
|
|
|
adc_hal_calibration_init(ADC_NUM_2);
|
|
|
|
return ret;
|
|
}
|
|
|
|
esp_err_t adc2_get_raw(adc2_channel_t channel, adc_bits_width_t width_bit, int *raw_out)
|
|
{
|
|
//On ESP32C3, the data width is always 12-bits.
|
|
if (width_bit != ADC_WIDTH_BIT_12) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
|
|
esp_err_t ret = ESP_OK;
|
|
|
|
periph_module_enable(PERIPH_SARADC_MODULE);
|
|
adc_power_acquire();
|
|
|
|
SAR_ADC2_LOCK_ACQUIRE();
|
|
|
|
adc_arbiter_t config = ADC_ARBITER_CONFIG_DEFAULT();
|
|
adc_hal_arbiter_config(&config);
|
|
|
|
adc_atten_t atten = s_atten2_single[channel];
|
|
uint32_t cal_val = adc_get_calibration_offset(ADC_NUM_2, channel, atten);
|
|
adc_hal_set_calibration_param(ADC_NUM_2, cal_val);
|
|
|
|
ADC_REG_LOCK_ENTER();
|
|
adc_hal_set_atten(ADC_NUM_2, channel, atten);
|
|
ret = adc_hal_convert(ADC_NUM_2, channel, raw_out);
|
|
ADC_REG_LOCK_EXIT();
|
|
|
|
SAR_ADC2_LOCK_RELEASE();
|
|
|
|
adc_power_release();
|
|
periph_module_disable(PERIPH_SARADC_MODULE);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/*************************************/
|
|
/* Digital controller filter setting */
|
|
/*************************************/
|
|
|
|
esp_err_t adc_digi_filter_reset(adc_digi_filter_idx_t idx)
|
|
{
|
|
ADC_ENTER_CRITICAL();
|
|
adc_hal_digi_filter_reset(idx);
|
|
ADC_EXIT_CRITICAL();
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t adc_digi_filter_set_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config)
|
|
{
|
|
ADC_ENTER_CRITICAL();
|
|
adc_hal_digi_filter_set_factor(idx, config);
|
|
ADC_EXIT_CRITICAL();
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t adc_digi_filter_get_config(adc_digi_filter_idx_t idx, adc_digi_filter_t *config)
|
|
{
|
|
ADC_ENTER_CRITICAL();
|
|
adc_hal_digi_filter_get_factor(idx, config);
|
|
ADC_EXIT_CRITICAL();
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t adc_digi_filter_enable(adc_digi_filter_idx_t idx, bool enable)
|
|
{
|
|
ADC_ENTER_CRITICAL();
|
|
adc_hal_digi_filter_enable(idx, enable);
|
|
ADC_EXIT_CRITICAL();
|
|
return ESP_OK;
|
|
}
|
|
|
|
/**************************************/
|
|
/* Digital controller monitor setting */
|
|
/**************************************/
|
|
|
|
esp_err_t adc_digi_monitor_set_config(adc_digi_monitor_idx_t idx, adc_digi_monitor_t *config)
|
|
{
|
|
ADC_ENTER_CRITICAL();
|
|
adc_hal_digi_monitor_config(idx, config);
|
|
ADC_EXIT_CRITICAL();
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t adc_digi_monitor_enable(adc_digi_monitor_idx_t idx, bool enable)
|
|
{
|
|
|
|
ADC_ENTER_CRITICAL();
|
|
adc_hal_digi_monitor_enable(idx, enable);
|
|
ADC_EXIT_CRITICAL();
|
|
return ESP_OK;
|
|
}
|
|
#endif //#if CONFIG_IDF_TARGET_ESP32C3
|
|
|
|
|
|
#if SOC_ADC_CALIBRATION_V1_SUPPORTED
|
|
/*---------------------------------------------------------------
|
|
Hardware Calibration Setting
|
|
---------------------------------------------------------------*/
|
|
#if CONFIG_IDF_TARGET_ESP32S2
|
|
#define esp_efuse_rtc_calib_get_ver() esp_efuse_rtc_table_read_calib_version()
|
|
|
|
static inline uint32_t esp_efuse_rtc_calib_get_init_code(int version, uint32_t adc_unit, int atten)
|
|
{
|
|
int tag = esp_efuse_rtc_table_get_tag(version, adc_unit + 1, atten, RTCCALIB_V2_PARAM_VINIT);
|
|
return esp_efuse_rtc_table_get_parsed_efuse_value(tag, false);
|
|
}
|
|
#endif
|
|
|
|
static uint16_t s_adc_cali_param[SOC_ADC_PERIPH_NUM][ADC_ATTEN_MAX] = {};
|
|
|
|
//NOTE: according to calibration version, different types of lock may be taken during the process:
|
|
// 1. Semaphore when reading efuse
|
|
// 2. Lock (Spinlock, or Mutex) if we actually do ADC calibration in the future
|
|
//This function shoudn't be called inside critical section or ISR
|
|
uint32_t adc_get_calibration_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten)
|
|
{
|
|
if (s_adc_cali_param[adc_n][atten]) {
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ESP_LOGV(ADC_TAG, "Use calibrated val ADC%d atten=%d: %04X", adc_n, atten, s_adc_cali_param[adc_n][atten]);
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return (uint32_t)s_adc_cali_param[adc_n][atten];
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|
}
|
|
|
|
// check if we can fetch the values from eFuse.
|
|
int version = esp_efuse_rtc_calib_get_ver();
|
|
|
|
uint32_t init_code = 0;
|
|
|
|
if (version == ESP_EFUSE_ADC_CALIB_VER) {
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|
init_code = esp_efuse_rtc_calib_get_init_code(version, adc_n, atten);
|
|
|
|
} else {
|
|
ESP_LOGD(ADC_TAG, "Calibration eFuse is not configured, use self-calibration for ICode");
|
|
adc_power_acquire();
|
|
ADC_ENTER_CRITICAL();
|
|
const bool internal_gnd = true;
|
|
init_code = adc_hal_self_calibration(adc_n, channel, atten, internal_gnd);
|
|
ADC_EXIT_CRITICAL();
|
|
adc_power_release();
|
|
}
|
|
|
|
s_adc_cali_param[adc_n][atten] = init_code;
|
|
ESP_LOGV(ADC_TAG, "Calib(V%d) ADC%d atten=%d: %04X", version, adc_n, atten, init_code);
|
|
|
|
return init_code;
|
|
}
|
|
|
|
// Internal function to calibrate PWDET for WiFi
|
|
esp_err_t adc_cal_offset(adc_ll_num_t adc_n, adc_channel_t channel, adc_atten_t atten)
|
|
{
|
|
adc_hal_calibration_init(adc_n);
|
|
uint32_t cal_val = adc_get_calibration_offset(adc_n, channel, atten);
|
|
ADC_ENTER_CRITICAL();
|
|
adc_hal_set_calibration_param(adc_n, cal_val);
|
|
ADC_EXIT_CRITICAL();
|
|
return ESP_OK;
|
|
}
|
|
#endif //#if SOC_ADC_CALIBRATION_V1_SUPPORTED
|
|
|
|
/*---------------------------------------------------------------
|
|
Deprecated API
|
|
---------------------------------------------------------------*/
|
|
#if CONFIG_IDF_TARGET_ESP32C3
|
|
#pragma GCC diagnostic ignored "-Wdeprecated-declarations"
|
|
#include "deprecated/driver/adc_deprecated.h"
|
|
#include "deprecated/driver/adc_types_deprecated.h"
|
|
esp_err_t adc_digi_controller_config(const adc_digi_config_t *config)
|
|
{
|
|
if (!s_adc_digi_ctx) {
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
ESP_RETURN_ON_FALSE((config->sample_freq_hz <= SOC_ADC_SAMPLE_FREQ_THRES_HIGH && config->sample_freq_hz >= SOC_ADC_SAMPLE_FREQ_THRES_LOW), ESP_ERR_INVALID_ARG, ADC_TAG, "DC sampling frequency out of range");
|
|
|
|
s_adc_digi_ctx->hal_digi_ctrlr_cfg.conv_limit_en = config->conv_limit_en;
|
|
s_adc_digi_ctx->hal_digi_ctrlr_cfg.conv_limit_num = config->conv_limit_num;
|
|
s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern_len = config->adc_pattern_len;
|
|
s_adc_digi_ctx->hal_digi_ctrlr_cfg.sample_freq_hz = config->sample_freq_hz;
|
|
|
|
for (int i = 0; i < config->adc_pattern_len; i++) {
|
|
s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern[i].atten = config->adc_pattern[i].atten;
|
|
s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern[i].channel = config->adc_pattern[i].channel;
|
|
s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern[i].unit = config->adc_pattern[i].unit;
|
|
}
|
|
|
|
|
|
const int atten_uninitialized = 999;
|
|
s_adc_digi_ctx->adc1_atten = atten_uninitialized;
|
|
s_adc_digi_ctx->adc2_atten = atten_uninitialized;
|
|
s_adc_digi_ctx->use_adc1 = 0;
|
|
s_adc_digi_ctx->use_adc2 = 0;
|
|
for (int i = 0; i < config->adc_pattern_len; i++) {
|
|
const adc_digi_pattern_config_t *pat = &s_adc_digi_ctx->hal_digi_ctrlr_cfg.adc_pattern[i];
|
|
if (pat->unit == ADC_NUM_1) {
|
|
s_adc_digi_ctx->use_adc1 = 1;
|
|
|
|
if (s_adc_digi_ctx->adc1_atten == atten_uninitialized) {
|
|
s_adc_digi_ctx->adc1_atten = pat->atten;
|
|
} else if (s_adc_digi_ctx->adc1_atten != pat->atten) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
} else if (pat->unit == ADC_NUM_2) {
|
|
//See whether ADC2 will be used or not. If yes, the ``sar_adc2_mutex`` should be acquired in the continuous read driver
|
|
s_adc_digi_ctx->use_adc2 = 1;
|
|
|
|
if (s_adc_digi_ctx->adc2_atten == atten_uninitialized) {
|
|
s_adc_digi_ctx->adc2_atten = pat->atten;
|
|
} else if (s_adc_digi_ctx->adc2_atten != pat->atten) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
}
|
|
}
|
|
|
|
return ESP_OK;
|
|
}
|
|
#endif //#if CONFIG_IDF_TARGET_ESP32C3
|