kopia lustrzana https://github.com/espressif/esp-idf
85 wiersze
3.3 KiB
C
85 wiersze
3.3 KiB
C
/*
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* SPDX-FileCopyrightText: 2021-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file cache_err_int.c
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* @brief The cache has an interrupt that can be raised as soon as an access to a cached
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* region (Flash, PSRAM) is done without the cache being enabled.
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* We use that here to panic the CPU, which from a debugging perspective,
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* is better than grabbing bad data from the bus.
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*/
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#include <stdint.h>
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#include "sdkconfig.h"
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#include "esp_err.h"
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#include "esp_log.h"
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#include "esp_attr.h"
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#include "esp_cpu.h"
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#include "esp_intr_alloc.h"
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#include "soc/soc.h"
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#include "soc/periph_defs.h"
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#include "esp_rom_sys.h"
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#include "hal/cache_ll.h"
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static const char *TAG = "CACHE_ERR";
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void esp_cache_err_int_init(void)
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{
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uint32_t core_id = esp_cpu_get_core_id();
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ESP_INTR_DISABLE(ETS_CACHEERR_INUM);
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// We do not register a handler for the interrupt because it is interrupt
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// level 4 which is not serviceable from C. Instead, xtensa_vectors.S has
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// a call to the panic handler for this interrupt.
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esp_rom_route_intr_matrix(core_id, ETS_CACHE_IA_INTR_SOURCE, ETS_CACHEERR_INUM);
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// Enable invalid cache access interrupt when the cache is disabled.
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// When the interrupt happens, we can not determine the CPU where the
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// invalid cache access has occurred. We enable the interrupt to catch
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// invalid access on both CPUs, but the interrupt is connected to the
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// CPU which happens to call this function.
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// For this reason, panic handler backtrace will not be correct if the
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// interrupt is connected to PRO CPU and invalid access happens on the APP CPU.
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ESP_DRAM_LOGV(TAG, "illegal error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ILG_EVENT_MASK);
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//illegal error intr doesn't depend on cache_id
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cache_ll_l1_clear_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK);
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cache_ll_l1_enable_illegal_error_intr(0, CACHE_LL_L1_ILG_EVENT_MASK);
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if (core_id == PRO_CPU_NUM) {
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esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE0_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
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/* On the hardware side, stat by clearing all the bits reponsible for
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* enabling cache access error interrupts. */
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ESP_DRAM_LOGV(TAG, "core 0 access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
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cache_ll_l1_clear_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
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cache_ll_l1_enable_access_error_intr(0, CACHE_LL_L1_ACCESS_EVENT_MASK);
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} else {
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esp_rom_route_intr_matrix(core_id, ETS_CACHE_CORE1_ACS_INTR_SOURCE, ETS_CACHEERR_INUM);
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/* On the hardware side, stat by clearing all the bits reponsible for
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* enabling cache access error interrupts. */
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ESP_DRAM_LOGV(TAG, "core 1 access error intr clr & ena mask is: 0x%x", CACHE_LL_L1_ACCESS_EVENT_MASK);
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cache_ll_l1_clear_access_error_intr(1, CACHE_LL_L1_ACCESS_EVENT_MASK);
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cache_ll_l1_enable_access_error_intr(1, CACHE_LL_L1_ACCESS_EVENT_MASK);
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}
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ESP_INTR_ENABLE(ETS_CACHEERR_INUM);
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}
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int esp_cache_err_get_cpuid(void)
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{
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if (cache_ll_l1_get_access_error_intr_status(0, CACHE_LL_L1_ACCESS_EVENT_MASK)) {
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return PRO_CPU_NUM;
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}
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if (cache_ll_l1_get_access_error_intr_status(1, CACHE_LL_L1_ACCESS_EVENT_MASK)) {
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return APP_CPU_NUM;
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}
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return -1;
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}
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