kopia lustrzana https://github.com/espressif/esp-idf
633 wiersze
24 KiB
C
633 wiersze
24 KiB
C
/*
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* SPDX-FileCopyrightText: 2023-2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @brief
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*
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* This file contains configuration APIs doing MSPI timing tuning by MSPI delay
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* This file will only be built, when `SOC_MEMSPI_TIMING_TUNING_BY_MSPI_DELAY == 1`
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*/
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#include <sys/param.h>
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#include "sdkconfig.h"
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#include "string.h"
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#include "esp_attr.h"
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#include "esp_err.h"
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#include "esp_types.h"
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#include "esp_log.h"
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#include "soc/rtc.h"
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#include "hal/mspi_timing_tuning_ll.h"
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#include "hal/clk_tree_ll.h"
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#include "hal/regi2c_ctrl_ll.h"
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#include "esp_private/mspi_timing_config.h"
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#include "mspi_timing_by_mspi_delay.h"
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#include "bootloader_flash.h"
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#include "esp32s3/rom/spi_flash.h"
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#include "esp32s3/rom/opi_flash.h"
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#define OPI_PSRAM_SYNC_READ 0x0000
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#define OPI_PSRAM_SYNC_WRITE 0x8080
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#define OCT_PSRAM_RD_DUMMY_NUM (2*(10-1))
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#define OCT_PSRAM_WR_DUMMY_NUM (2*(5-1))
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#define QPI_PSRAM_FAST_READ 0XEB
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#define QPI_PSRAM_WRITE 0X38
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#define QPI_PSRAM_FAST_READ_DUMMY 6
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#define NOT_INIT_INT 127
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/////////////////////////////////////////TIMING TUNING IS NEEDED//////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////////////////////////////////////
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#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
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const static char *TAG = "MSPI Timing";
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//If one of the FLASH / PSRAM or both of them need timing tuning, we should build following code
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typedef enum {
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PSRAM_CMD_QPI,
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PSRAM_CMD_SPI,
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} psram_cmd_mode_t;
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static uint8_t s_rom_flash_extra_dummy[2] = {NOT_INIT_INT, NOT_INIT_INT};
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#if CONFIG_SPIRAM_MODE_QUAD
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static uint8_t s_psram_extra_dummy;
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extern void psram_exec_cmd(int spi_num, psram_cmd_mode_t mode,
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uint32_t cmd, int cmd_bit_len,
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uint32_t addr, int addr_bit_len,
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int dummy_bits,
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uint8_t* mosi_data, int mosi_bit_len,
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uint8_t* miso_data, int miso_bit_len,
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uint32_t cs_mask,
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bool is_write_erase_operation);
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#endif
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//-------------------------------------FLASH timing tuning register config-------------------------------------//
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void mspi_timing_get_flash_tuning_configs(mspi_timing_config_t *config)
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{
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#if MSPI_TIMING_FLASH_DTR_MODE
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#define FLASH_MODE DTR_MODE
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#else //MSPI_TIMING_FLASH_STR_MODE
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#define FLASH_MODE STR_MODE
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#endif
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#if CONFIG_ESPTOOLPY_FLASHFREQ_80M
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*config = MSPI_TIMING_FLASH_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 80, FLASH_MODE);
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#elif CONFIG_ESPTOOLPY_FLASHFREQ_120M
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*config = MSPI_TIMING_FLASH_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 120, FLASH_MODE);
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#else
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assert(false && "should never reach here");
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#endif
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#undef FLASH_MODE
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}
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void mspi_timing_flash_init(uint32_t flash_freq_mhz)
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{
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mspi_timing_config_set_flash_clock(flash_freq_mhz, MSPI_TIMING_SPEED_MODE_NORMAL_PERF, true);
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//Power on HCLK
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mspi_timinng_ll_enable_flash_hclk(0);
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}
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static void s_set_flash_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num)
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{
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mspi_timing_ll_set_flash_din_mode(spi_num, din_mode);
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mspi_timing_ll_set_flash_din_num(spi_num, din_num);
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}
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static uint32_t spi_timing_config_get_dummy(void)
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{
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mspi_timing_ll_flash_mode_t mode = mspi_timing_ll_get_flash_mode(0);
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if (mode == MSPI_TIMING_LL_FLASH_OPI_MODE) {
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abort();
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}
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#if CONFIG_SPI_FLASH_HPM_DC_ON
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if (spi_flash_hpm_dummy_adjust()) { // HPM-DC is enabled
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const spi_flash_hpm_dummy_conf_t *hpm_dummy = spi_flash_hpm_get_dummy();
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switch (mode) {
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case MSPI_TIMING_LL_FLASH_QIO_MODE:
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return hpm_dummy->qio_dummy - 1;
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case MSPI_TIMING_LL_FLASH_QUAD_MODE:
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return hpm_dummy->qout_dummy - 1;
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case MSPI_TIMING_LL_FLASH_DIO_MODE:
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return hpm_dummy->dio_dummy - 1;
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case MSPI_TIMING_LL_FLASH_DUAL_MODE:
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return hpm_dummy->dout_dummy - 1;
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case MSPI_TIMING_LL_FLASH_FAST_MODE:
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return hpm_dummy->fastrd_dummy - 1;
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case MSPI_TIMING_LL_FLASH_SLOW_MODE:
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return 0;
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default:
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abort();
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}
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} else
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#endif
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{ // HPM-DC is not enabled
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switch (mode) {
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case MSPI_TIMING_LL_FLASH_QIO_MODE:
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return SPI1_R_QIO_DUMMY_CYCLELEN;
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case MSPI_TIMING_LL_FLASH_QUAD_MODE:
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return SPI1_R_FAST_DUMMY_CYCLELEN;
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case MSPI_TIMING_LL_FLASH_DIO_MODE:
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return SPI1_R_DIO_DUMMY_CYCLELEN;
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case MSPI_TIMING_LL_FLASH_DUAL_MODE:
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return SPI1_R_FAST_DUMMY_CYCLELEN;
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case MSPI_TIMING_LL_FLASH_FAST_MODE:
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return SPI1_R_FAST_DUMMY_CYCLELEN;
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case MSPI_TIMING_LL_FLASH_SLOW_MODE:
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return 0;
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default:
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abort();
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}
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}
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}
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static void s_set_flash_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
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{
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if (bootloader_flash_is_octal_mode_enabled()) {
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mspi_timing_ll_set_octal_flash_extra_dummy(spi_num, extra_dummy);
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return;
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}
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/**
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* HW workaround:
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* The `SPI_MEM_TIMING_CALI_REG` register is only used for OPI on 728
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* Here we only need to update this global variable for extra dummy. Since we use the ROM Flash API, which will set the dummy based on this.
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* We only initialise the SPI0. And leave the SPI1 for flash driver to configure.
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*/
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if (s_rom_flash_extra_dummy[spi_num] == NOT_INIT_INT) {
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s_rom_flash_extra_dummy[spi_num] = g_rom_spiflash_dummy_len_plus[spi_num];
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}
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g_rom_spiflash_dummy_len_plus[spi_num] = s_rom_flash_extra_dummy[spi_num] + extra_dummy;
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// Only Quad Flash will run into this branch.
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uint32_t dummy = spi_timing_config_get_dummy();
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mspi_timing_ll_set_quad_flash_dummy(spi_num, dummy + g_rom_spiflash_dummy_len_plus[spi_num]);
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}
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void mspi_timing_config_flash_set_tuning_regs(const void *configs, uint8_t id)
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{
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const mspi_timing_tuning_param_t *params = &((mspi_timing_config_t *)configs)->tuning_config_table[id];
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/**
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* 1. SPI_MEM_DINx_MODE(1), SPI_MEM_DINx_NUM(1) are meaningless
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* SPI0 and SPI1 share the SPI_MEM_DINx_MODE(0), SPI_MEM_DINx_NUM(0) for FLASH timing tuning
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* 2. We use SPI1 to get the best Flash timing tuning (mode and num) config
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*/
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s_set_flash_din_mode_num(0, params->spi_din_mode, params->spi_din_num);
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s_set_flash_extra_dummy(1, params->extra_dummy_len);
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}
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//-------------------------------------------FLASH Read/Write------------------------------------------//
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void mspi_timing_config_flash_read_data(uint8_t *buf, uint32_t addr, uint32_t len)
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{
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if (bootloader_flash_is_octal_mode_enabled()) {
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// note that in spi_flash_read API, there is a wait-idle stage, since flash can only be read in idle state.
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// but after we change the timing settings, we might not read correct idle status via RDSR.
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// so, here we should use a read API that won't check idle status.
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mspi_timing_ll_clear_fifo(1);
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esp_rom_opiflash_read_raw(addr, buf, len);
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} else {
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esp_rom_spiflash_read(addr, (uint32_t *)buf, len);
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}
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}
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//-------------------------------------PSRAM timing tuning register config-------------------------------------//
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void mspi_timing_get_psram_tuning_configs(mspi_timing_config_t *config)
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{
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#if MSPI_TIMING_PSRAM_DTR_MODE
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#define PSRAM_MODE DTR_MODE
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#else //MSPI_TIMING_PSRAM_STR_MODE
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#define PSRAM_MODE STR_MODE
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#endif
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#if CONFIG_SPIRAM_SPEED_80M
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*config = MSPI_TIMING_PSRAM_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 80, PSRAM_MODE);
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#elif CONFIG_SPIRAM_SPEED_120M
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*config = MSPI_TIMING_PSRAM_GET_TUNING_CONFIG(MSPI_TIMING_CORE_CLOCK_MHZ, 120, PSRAM_MODE);
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#else
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assert(false && "should never reach here");
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#endif
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#undef PSRAM_MODE
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}
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void mspi_timing_psram_init(uint32_t psram_freq_mhz)
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{
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mspi_timing_config_set_flash_clock(psram_freq_mhz, MSPI_TIMING_SPEED_MODE_NORMAL_PERF, true);
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//Power on HCLK
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mspi_timinng_ll_enable_psram_hclk(0);
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}
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static void s_set_psram_din_mode_num(uint8_t spi_num, uint8_t din_mode, uint8_t din_num)
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{
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mspi_timing_ll_set_psram_din_mode(spi_num, din_mode);
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mspi_timing_ll_set_psram_din_num(spi_num, din_num);
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}
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static void s_set_psram_extra_dummy(uint8_t spi_num, uint8_t extra_dummy)
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{
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#if CONFIG_SPIRAM_MODE_OCT
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mspi_timing_ll_set_octal_psram_extra_dummy(spi_num, extra_dummy);
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#elif CONFIG_SPIRAM_MODE_QUAD
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//HW workaround: Use normal dummy register to set extra dummy, the calibration dedicated extra dummy register doesn't work for quad mode
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mspi_timing_ll_set_quad_psram_dummy(spi_num, (QPI_PSRAM_FAST_READ_DUMMY + extra_dummy - 1));
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#endif
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}
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void mspi_timing_config_psram_set_tuning_regs(const void *configs, uint8_t id)
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{
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const mspi_timing_tuning_param_t *params = &((mspi_timing_config_t *)configs)->tuning_config_table[id];
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/**
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* 1. SPI_MEM_SPI_SMEM_DINx_MODE(1), SPI_MEM_SPI_SMEM_DINx_NUM(1) are meaningless
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* SPI0 and SPI1 share the SPI_MEM_SPI_SMEM_DINx_MODE(0), SPI_MEM_SPI_SMEM_DINx_NUM(0) for PSRAM timing tuning
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* 2. We use SPI1 to get the best PSRAM timing tuning (mode and num) config
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*/
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s_set_psram_din_mode_num(0, params->spi_din_mode, params->spi_din_num);
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#if CONFIG_SPIRAM_MODE_OCT
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//On 728, for SPI1, flash and psram share the extra dummy register
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s_set_flash_extra_dummy(1, params->extra_dummy_len);
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#elif CONFIG_SPIRAM_MODE_QUAD
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//Update this `s_psram_extra_dummy`, the `s_psram_read_data` will set dummy according to this `s_psram_extra_dummy`
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s_psram_extra_dummy = params->extra_dummy_len;
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mspi_timing_ll_set_quad_flash_dummy(1, params->extra_dummy_len - 1);
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#endif
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}
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//-------------------------------------------PSRAM Read/Write------------------------------------------//
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static void s_psram_write_data(uint8_t *buf, uint32_t addr, uint32_t len)
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{
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#if CONFIG_SPIRAM_MODE_OCT
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esp_rom_opiflash_exec_cmd(1, ESP_ROM_SPIFLASH_OPI_DTR_MODE,
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OPI_PSRAM_SYNC_WRITE, 16,
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addr, 32,
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OCT_PSRAM_WR_DUMMY_NUM,
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buf, len * 8,
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NULL, 0,
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BIT(1),
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false);
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#elif CONFIG_SPIRAM_MODE_QUAD
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psram_exec_cmd(1, 0,
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QPI_PSRAM_WRITE, 8,
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addr, 24,
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0,
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buf, len * 8,
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NULL, 0,
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SPI_MEM_CS1_DIS_M,
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false);
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#endif
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}
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static void s_psram_read_data(uint8_t *buf, uint32_t addr, uint32_t len)
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{
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#if CONFIG_SPIRAM_MODE_OCT
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mspi_timing_ll_clear_fifo(1);
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esp_rom_opiflash_exec_cmd(1, ESP_ROM_SPIFLASH_OPI_DTR_MODE,
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OPI_PSRAM_SYNC_READ, 16,
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addr, 32,
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OCT_PSRAM_RD_DUMMY_NUM,
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NULL, 0,
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buf, len * 8,
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BIT(1),
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false);
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#elif CONFIG_SPIRAM_MODE_QUAD
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psram_exec_cmd(1, 0,
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QPI_PSRAM_FAST_READ, 8,
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addr, 24,
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QPI_PSRAM_FAST_READ_DUMMY + s_psram_extra_dummy,
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NULL, 0,
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buf, len * 8,
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SPI_MEM_CS1_DIS_M,
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false);
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#endif
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}
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static void s_psram_execution(uint8_t *buf, uint32_t addr, uint32_t len, bool is_read)
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{
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while (len) {
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uint32_t length = MIN(len, 32);
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if (is_read) {
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s_psram_read_data(buf, addr, length);
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} else {
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s_psram_write_data(buf, addr, length);
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}
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addr += length;
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buf += length;
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len -= length;
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}
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}
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void mspi_timing_config_psram_prepare_reference_data(uint8_t *buf, uint32_t len)
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{
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assert((len == MSPI_TIMING_TEST_DATA_LEN) && (len % 4 == 0));
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for (int i=0; i < len/4; i++) {
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((uint32_t *)buf)[i] = 0xa5ff005a;
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}
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}
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void mspi_timing_config_psram_write_data(uint8_t *buf, uint32_t addr, uint32_t len)
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{
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s_psram_execution(buf, addr, len, false);
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}
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void mspi_timing_config_psram_read_data(uint8_t *buf, uint32_t addr, uint32_t len)
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{
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s_psram_execution(buf, addr, len, true);
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}
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/*-------------------------------------------------------------------------------------------------
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* Best Timing Tuning Params Selection
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*-------------------------------------------------------------------------------------------------*/
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#if (MSPI_TIMING_FLASH_DTR_MODE || MSPI_TIMING_PSRAM_DTR_MODE) && (MSPI_TIMING_CORE_CLOCK_MHZ == 240)
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static bool get_working_pll_freq(const uint8_t *reference_data, bool is_flash, uint32_t *out_max_freq, uint32_t *out_min_freq)
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{
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uint8_t read_data[MSPI_TIMING_TEST_DATA_LEN] = {0};
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rtc_cpu_freq_config_t previous_config;
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rtc_clk_cpu_freq_get_config(&previous_config);
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uint32_t big_num = MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX * 2; //This number should be larger than MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX, for error handling
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uint32_t max_freq = 0;
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uint32_t min_freq = big_num;
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soc_xtal_freq_t xtal_freq = rtc_clk_xtal_freq_get();
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for (int pll_mhz_tuning = MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MIN; pll_mhz_tuning <= MSPI_TIMING_PLL_FREQ_SCAN_RANGE_MHZ_MAX; pll_mhz_tuning += 8) {
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//bbpll calibration start
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regi2c_ctrl_ll_bbpll_calibration_start();
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/**
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* pll_mhz = xtal_mhz * (oc_div + 4) / (oc_ref_div + 1)
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*/
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clk_ll_bbpll_set_frequency_for_mspi_tuning(xtal_freq, pll_mhz_tuning, ((pll_mhz_tuning / 4) - 4), 9);
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//wait calibration done
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while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
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//bbpll calibration stop
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regi2c_ctrl_ll_bbpll_calibration_stop();
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memset(read_data, 0, MSPI_TIMING_TEST_DATA_LEN);
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if (is_flash) {
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mspi_timing_config_flash_read_data(read_data, MSPI_TIMING_FLASH_TEST_DATA_ADDR, MSPI_TIMING_TEST_DATA_LEN);
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} else {
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mspi_timing_config_psram_read_data(read_data, MSPI_TIMING_PSRAM_TEST_DATA_ADDR, MSPI_TIMING_TEST_DATA_LEN);
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}
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if (memcmp(read_data, reference_data, MSPI_TIMING_TEST_DATA_LEN) == 0) {
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max_freq = MAX(pll_mhz_tuning, max_freq);
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min_freq = MIN(pll_mhz_tuning, min_freq);
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//Continue to find successful cases
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continue;
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}
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if (max_freq != 0) {
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//The first fail case after successful case(s) is the end
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break;
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}
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//If no break, no successful case found, continue to find successful cases
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}
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//restore PLL config
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clk_ll_bbpll_set_freq_mhz(previous_config.source_freq_mhz);
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//bbpll calibration start
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regi2c_ctrl_ll_bbpll_calibration_start();
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//set pll
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clk_ll_bbpll_set_config(previous_config.source_freq_mhz, xtal_freq);
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//wait calibration done
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while(!regi2c_ctrl_ll_bbpll_calibration_is_done());
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//bbpll calibration stop
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regi2c_ctrl_ll_bbpll_calibration_stop();
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*out_max_freq = max_freq;
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*out_min_freq = min_freq;
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return (max_freq != 0);
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}
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#endif //Frequency Scanning
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static uint32_t s_select_best_tuning_config_dtr(const mspi_timing_config_t *configs, uint32_t consecutive_length, uint32_t end, const uint8_t *reference_data, bool is_flash)
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{
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#if (MSPI_TIMING_CORE_CLOCK_MHZ == 160)
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//Core clock 160M DTR best point scheme
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uint32_t best_point;
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//Define these magic number in macros in `spi_timing_config.h`. TODO: IDF-3663
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if (consecutive_length <= 2 || consecutive_length >= 6) {
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//tuning is FAIL, select default point, and generate a warning
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best_point = configs->default_config_id;
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ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %"PRIu32"", best_point);
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} else if (consecutive_length <= 4) {
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//consecutive length : 3 or 4
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best_point = end - 1;
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ESP_EARLY_LOGD(TAG, "tuning success, best point is index %"PRIu32"", best_point);
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} else {
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//consecutive point list length equals 5
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best_point = end - 2;
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ESP_EARLY_LOGD(TAG, "tuning success, best point is index %"PRIu32"", best_point);
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}
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return best_point;
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#elif (MSPI_TIMING_CORE_CLOCK_MHZ == 240)
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uint32_t best_point = 0;
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uint32_t current_point = end + 1 - consecutive_length;
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bool ret = false;
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//This `max_freq` is the max pll frequency that per MSPI timing tuning config can work
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uint32_t max_freq = 0;
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uint32_t temp_max_freq = 0;
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uint32_t temp_min_freq = 0;
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for (; current_point <= end; current_point++) {
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if (is_flash) {
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mspi_timing_config_flash_set_tuning_regs(configs, current_point);
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} else {
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mspi_timing_config_psram_set_tuning_regs(configs, current_point);
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}
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ret = get_working_pll_freq(reference_data, is_flash, &temp_max_freq, &temp_min_freq);
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if (ret && temp_min_freq <= MSPI_TIMING_PLL_FREQ_SCAN_THRESH_MHZ_LOW && temp_max_freq >= MSPI_TIMING_PLL_FREQ_SCAN_THRESH_MHZ_HIGH && temp_max_freq > max_freq) {
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max_freq = temp_max_freq;
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best_point = current_point;
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}
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ESP_EARLY_LOGD(TAG, "sample point %" PRIu32 ", max pll is %" PRIu32 " mhz, min pll is %" PRIu32, current_point, temp_max_freq, temp_min_freq);
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}
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if (max_freq == 0) {
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ESP_EARLY_LOGW(TAG, "freq scan tuning fail, best point is fallen back to index %" PRIu32, end + 1 - consecutive_length);
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best_point = end + 1 - consecutive_length;
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} else {
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ESP_EARLY_LOGD(TAG, "freq scan success, max pll is %" PRIu32 "mhz, best point is index %" PRIu32, max_freq, best_point);
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}
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return best_point;
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#else
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//won't reach here
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abort();
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#endif
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}
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static uint32_t s_select_best_tuning_config_str(const mspi_timing_config_t *configs, uint32_t consecutive_length, uint32_t end)
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{
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#if (MSPI_TIMING_CORE_CLOCK_MHZ == 120 || MSPI_TIMING_CORE_CLOCK_MHZ == 240)
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//STR best point scheme
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uint32_t best_point;
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if (consecutive_length <= 2|| consecutive_length >= 5) {
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//tuning is FAIL, select default point, and generate a warning
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best_point = configs->default_config_id;
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ESP_EARLY_LOGW(TAG, "tuning fail, best point is fallen back to index %"PRIu32"", best_point);
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} else {
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//consecutive length : 3 or 4
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best_point = end - consecutive_length / 2;
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ESP_EARLY_LOGD(TAG, "tuning success, best point is index %"PRIu32"", best_point);
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}
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return best_point;
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#else
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//won't reach here
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abort();
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#endif
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}
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static uint32_t s_select_best_tuning_config(const mspi_timing_config_t *configs, uint32_t consecutive_length, uint32_t end, const uint8_t *reference_data, bool is_ddr, bool is_flash)
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{
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uint32_t best_point = 0;
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if (is_ddr) {
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best_point = s_select_best_tuning_config_dtr(configs, consecutive_length, end, reference_data, is_flash);
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} else {
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best_point = s_select_best_tuning_config_str(configs, consecutive_length, end);
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}
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return best_point;
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}
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uint32_t mspi_timing_flash_select_best_tuning_config(const void *configs, uint32_t consecutive_length, uint32_t end, const uint8_t *reference_data, bool is_ddr)
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{
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const mspi_timing_config_t *timing_configs = (const mspi_timing_config_t *)configs;
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uint32_t best_point = s_select_best_tuning_config(timing_configs, consecutive_length, end, reference_data, is_ddr, true);
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ESP_EARLY_LOGI(TAG, "Flash timing tuning index: %"PRIu32"", best_point);
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return best_point;
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}
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uint32_t mspi_timing_psram_select_best_tuning_config(const void *configs, uint32_t consecutive_length, uint32_t end, const uint8_t *reference_data, bool is_ddr)
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{
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const mspi_timing_config_t *timing_configs = (const mspi_timing_config_t *)configs;
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uint32_t best_point = s_select_best_tuning_config(timing_configs, consecutive_length, end, reference_data, is_ddr, false);
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ESP_EARLY_LOGI(TAG, "PSRAM timing tuning index: %"PRIu32"", best_point);
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return best_point;
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}
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static mspi_timing_tuning_param_t s_flash_best_timing_tuning_config;
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static mspi_timing_tuning_param_t s_psram_best_timing_tuning_config;
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void mspi_timing_flash_set_best_tuning_config(const void *configs, uint8_t best_id)
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{
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s_flash_best_timing_tuning_config = ((const mspi_timing_config_t *)configs)->tuning_config_table[best_id];
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}
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void mspi_timing_psram_set_best_tuning_config(const void *configs, uint8_t best_id)
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{
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s_psram_best_timing_tuning_config = ((const mspi_timing_config_t *)configs)->tuning_config_table[best_id];
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}
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|
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/*-------------------------------------------------------------------------------------------------
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* Best Timing Tuning Params Clear / Set
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*-------------------------------------------------------------------------------------------------*/
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void mspi_timing_flash_config_clear_tuning_regs(bool control_both_mspi)
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{
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s_set_flash_din_mode_num(0, 0, 0); //SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg
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s_set_flash_extra_dummy(0, 0);
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//Won't touch SPI1 registers if not control_both_mspi
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if (control_both_mspi) {
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s_set_flash_extra_dummy(1, 0);
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}
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}
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void mspi_timing_flash_config_set_tuning_regs(bool control_both_mspi)
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{
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//SPI0 and SPI1 share the registers for flash din mode and num setting, so we only set SPI0's reg
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s_set_flash_din_mode_num(0, s_flash_best_timing_tuning_config.spi_din_mode, s_flash_best_timing_tuning_config.spi_din_num);
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s_set_flash_extra_dummy(0, s_flash_best_timing_tuning_config.extra_dummy_len);
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if (control_both_mspi) {
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s_set_flash_extra_dummy(1, s_flash_best_timing_tuning_config.extra_dummy_len);
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} else {
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|
//Won't touch SPI1 registers
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|
}
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|
}
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|
|
|
void mspi_timing_psram_config_clear_tuning_regs(bool control_both_mspi)
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|
{
|
|
(void)control_both_mspi; //for compatibility
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|
s_set_psram_din_mode_num(0, 0, 0);
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|
s_set_psram_extra_dummy(0, 0);
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}
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|
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|
void mspi_timing_psram_config_set_tuning_regs(bool control_both_mspi)
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|
{
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|
(void)control_both_mspi; //for compatibility
|
|
s_set_psram_din_mode_num(0, s_psram_best_timing_tuning_config.spi_din_mode, s_psram_best_timing_tuning_config.spi_din_num);
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|
s_set_psram_extra_dummy(0, s_psram_best_timing_tuning_config.extra_dummy_len);
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|
}
|
|
#endif //#if MSPI_TIMING_FLASH_NEEDS_TUNING || MSPI_TIMING_PSRAM_NEEDS_TUNING
|
|
|
|
|
|
/*-------------------------------------------------------------------------------------------------
|
|
* To let upper lay (spi_flash_timing_tuning.c) to know the necessary timing registers
|
|
*-------------------------------------------------------------------------------------------------*/
|
|
/**
|
|
* Get the SPI1 Flash CS timing setting. The setup time and hold time are both realistic cycles.
|
|
* @note On ESP32-S3, SPI0/1 share the Flash CS timing registers. Therefore, we should not change these values.
|
|
* @note This function inform `spi_flash_timing_tuning.c` (driver layer) of the cycle,
|
|
* and other component (esp_flash driver) should get these cycle and configure the registers accordingly.
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|
*/
|
|
void mspi_timing_config_get_cs_timing(uint8_t *setup_time, uint32_t *hold_time)
|
|
{
|
|
*setup_time = mspi_timing_ll_get_cs_setup_val(0);
|
|
*hold_time = mspi_timing_ll_get_cs_hold_val(0);
|
|
/**
|
|
* The logic here is, if setup_en / hold_en is false, then we return the realistic cycle number,
|
|
* which is 0. If true, then the realistic cycle number is (reg_value + 1)
|
|
*/
|
|
if (mspi_timing_ll_is_cs_setup_enabled(0)) {
|
|
*setup_time += 1;
|
|
} else {
|
|
*setup_time = 0;
|
|
}
|
|
if (mspi_timing_ll_is_cs_hold_enabled(0)) {
|
|
*hold_time += 1;
|
|
} else {
|
|
*hold_time = 0;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* Get the SPI1 Flash clock setting.
|
|
* @note Similarly, this function inform `spi_flash_timing_tuning.c` (driver layer) of the clock setting,
|
|
* and other component (esp_flash driver) should get these and configure the registers accordingly.
|
|
*/
|
|
uint32_t mspi_timing_config_get_flash_clock_reg(void)
|
|
{
|
|
return mspi_timing_ll_get_clock_reg(1);
|
|
}
|
|
|
|
uint8_t mspi_timing_config_get_flash_extra_dummy(void)
|
|
{
|
|
#if MSPI_TIMING_FLASH_NEEDS_TUNING
|
|
return s_flash_best_timing_tuning_config.extra_dummy_len;
|
|
#else
|
|
return 0;
|
|
#endif
|
|
}
|