kopia lustrzana https://github.com/espressif/esp-idf
362 wiersze
14 KiB
C
362 wiersze
14 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdint.h>
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#include <stdlib.h>
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#include "soc/soc.h"
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#include "soc/rtc.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/syscon_reg.h"
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#include "soc/i2s_reg.h"
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#include "soc/bb_reg.h"
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#include "soc/nrx_reg.h"
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#include "soc/fe_reg.h"
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#include "soc/timer_group_reg.h"
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#include "soc/system_reg.h"
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#include "esp32h2/rom/ets_sys.h"
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#include "esp32h2/rom/rtc.h"
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#include "regi2c_ctrl.h"
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#include "regi2c_bias.h"
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#include "regi2c_ulp.h"
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#include "esp_efuse.h"
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#include "i2c_pmu.h"
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#include "esp_hw_log.h"
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#include "esp_rom_uart.h"
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#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
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#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIG_REGULATOR_REG
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#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_DIG_REGULATOR_REG
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#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
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#define RTC_CNTL_DIG_REGULATOR_REG1 RTC_CNTL_DIGULATOR_REG
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#define RTC_CNTL_DIG_REGULATOR_REG2 RTC_CNTL_REG
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#define RTC_CNTL_DIG_REGULATOR1_DBIAS_REG RTC_CNTL_DIGULATOR1_DBIAS_REG
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#define RTC_CNTL_DIG_REGULATOR0_DBIAS_REG RTC_CNTL_DIGULATOR0_DBIAS_REG
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#define RTC_CNTL_REGULATOR1_DBIAS_REG RTC_CNTL_RTCULATOR1_DBIAS_REG
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#define RTC_CNTL_REGULATOR0_DBIAS_REG RTC_CNTL_RTCULATOR0_DBIAS_REG
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#endif
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/**
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* Configure whether certain peripherals are powered down in deep sleep
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* @param cfg power down flags as rtc_sleep_pu_config_t structure
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*/
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static const char *TAG = "rtc_sleep";
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void rtc_sleep_pu(rtc_sleep_pu_config_t cfg)
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{
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REG_SET_FIELD(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_LSLP_MEM_FORCE_PU, cfg.dig_fpu);
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REG_SET_FIELD(RTC_CNTL_PWC_REG, RTC_CNTL_FASTMEM_FORCE_LPU, cfg.rtc_fpu);
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REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_DC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_PBUS_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(SYSCON_FRONT_END_MEM_PD_REG, SYSCON_AGC_MEM_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(BBPD_CTRL, BB_FFT_FORCE_PU, cfg.bb_fpu);
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REG_SET_FIELD(BBPD_CTRL, BB_DC_EST_FORCE_PU, cfg.bb_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_RX_ROT_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_VIT_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(NRXPD_CTRL, NRX_DEMAP_FORCE_PU, cfg.nrx_fpu);
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REG_SET_FIELD(FE_GEN_CTRL, FE_IQ_EST_FORCE_PU, cfg.fe_fpu);
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REG_SET_FIELD(FE2_TX_INTERP_CTRL, FE2_TX_INF_FORCE_PU, cfg.fe_fpu);
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if (cfg.sram_fpu) {
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, SYSCON_SRAM_POWER_UP);
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} else {
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_SRAM_POWER_UP, 0);
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}
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if (cfg.rom_ram_fpu) {
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, SYSCON_ROM_POWER_UP);
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} else {
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REG_SET_FIELD(SYSCON_MEM_POWER_UP_REG, SYSCON_ROM_POWER_UP, 0);
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}
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}
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void dcdc_ctl(uint32_t mode)
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{
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REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_IDLE, RTC_CNTL_DCDC_TRX_MODE);
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REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_MONITOR, RTC_CNTL_DCDC_TRX_MODE);
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if ((mode & 0x10) == 0x10) {
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REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, mode);
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} else if (mode == 0) {
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REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, RTC_CNTL_DCDC_TRX_MODE);
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} else if (mode == 1) {
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REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, RTC_CNTL_DCDC_LSLP_MODE);
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} else if (mode == 2) {
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REG_SET_FIELD(RTC_CNTL_DCDC_CTRL1_REG, RTC_CNTL_DCDC_MODE_SLP, RTC_CNTL_DCDC_DSLP_MODE);
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} else {
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ESP_HW_LOGE(TAG, "invalid dcdc mode!\n");
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}
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}
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void regulator_set(regulator_cfg_t cfg)
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{
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// DIG REGULATOR0
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if (cfg.dig_regul0_en) {
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PD, 0);
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} else {
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PU, 0);
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_FORCE_PD, 1);
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}
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// DIG REGULATOR1
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if (cfg.dig_regul1_en) {
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 0);
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} else {
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PU, 0);
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_REGULATOR_SLP_FORCE_PD, 1);
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}
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// RTC REGULATOR0
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if (cfg.rtc_regul0_en) {
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU, 0);
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PD, 0);
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} else {
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU, 0);
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PD, 1);
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}
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}
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void regulator_slt(regulator_config_t regula_cfg)
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{
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// dig regulator
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if (regula_cfg.dig_source == 1) {
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_SLP, regula_cfg.dig_slp_dbias);
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR1_DBIAS_REG, RTC_CNTL_DIG_REGULATOR1_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
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} else {
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_SLP, regula_cfg.dig_slp_dbias);
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR0_DBIAS_REG, RTC_CNTL_DIG_REGULATOR0_DBIAS_ACTIVE, regula_cfg.dig_active_dbias);
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}
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// rtc regulator
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if (regula_cfg.rtc_source == 1) {
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REG_SET_FIELD(RTC_CNTL_REGULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
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REG_SET_FIELD(RTC_CNTL_REGULATOR1_DBIAS_REG, RTC_CNTL_REGULATOR1_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
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} else {
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REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_SLP, regula_cfg.rtc_slp_dbias);
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REG_SET_FIELD(RTC_CNTL_REGULATOR0_DBIAS_REG, RTC_CNTL_REGULATOR0_DBIAS_ACTIVE, regula_cfg.rtc_active_dbias);
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}
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}
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void dbias_switch_set(dbias_swt_cfg_t cfg)
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{
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_IDLE, cfg.swt_idle);
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_MONITOR, cfg.swt_monitor);
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_DBIAS_SWITCH_SLP, cfg.swt_slp);
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}
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void left_up_trx_fpu(bool fpu)
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{
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if (fpu) {
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REGI2C_WRITE_MASK(I2C_BIAS, I2C_BIAS_FORCE_DISABLE_BIAS_SLEEP, 0);
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_BIAS_BUF, 0);
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REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_IPH, 0);
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SET_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_XPD_TRX_FORCE_PU);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG, RTC_CNTL_XPD_TRX_FORCE_PU);
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}
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}
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void rtc_sleep_pmu_init(void)
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{
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dcdc_ctl(DCDC_SLP_DSLP_MODE);
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dbias_swt_cfg_t swt_cfg = DBIAS_SWITCH_CONFIG_DEFAULT();
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dbias_switch_set(swt_cfg);
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regulator_config_t regula0_cfg = REGULATOR0_CONFIG_DEFAULT();
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regulator_slt(regula0_cfg);
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regulator_config_t regula1_cfg = REGULATOR1_CONFIG_DEFAULT();
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regulator_slt(regula1_cfg);
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regulator_cfg_t rg_set = REGULATOR_SET_DEFAULT();
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regulator_set(rg_set);
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left_up_trx_fpu(0);
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}
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void rtc_sleep_init(rtc_sleep_config_t cfg)
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{
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if (cfg.lslp_mem_inf_fpu) {
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rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
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rtc_sleep_pu(pu_cfg);
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}
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if (cfg.bt_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_BT_PD_EN);
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}
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if (cfg.cpu_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_CPU_TOP_PD_EN);
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}
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if (cfg.dig_peri_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_PERI_PD_EN);
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}
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if (cfg.dig_ret_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_RET_PD_EN);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_RET_PD_EN);
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}
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_MONITOR, RTC_CNTL_BIASSLP_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_BIAS_SLEEP_DEEP_SLP, RTC_CNTL_BIASSLP_SLEEP_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_MONITOR, RTC_CNTL_PD_CUR_MONITOR_DEFAULT);
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REG_SET_FIELD(RTC_CNTL_BIAS_CONF_REG, RTC_CNTL_PD_CUR_DEEP_SLP, RTC_CNTL_PD_CUR_SLEEP_DEFAULT);
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// ESP32-H2 TO-DO: IDF-3693
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if (cfg.deep_slp) {
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// REGI2C_WRITE_MASK(I2C_ULP, I2C_ULP_IR_FORCE_XPD_CK, 0);
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// CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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CLEAR_PERI_REG_MASK(RTC_CNTL_ANA_CONF_REG,
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RTC_CNTL_CKGEN_I2C_PU | RTC_CNTL_PLL_I2C_PU |
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RTC_CNTL_RFRX_PBUS_PU | RTC_CNTL_TXRF_I2C_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_OPTIONS0_REG, RTC_CNTL_BB_I2C_FORCE_PU);
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} else {
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SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_VDD_DRV_B_SLP_EN);
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REG_SET_FIELD(RTC_CNTL_DIG_REGULATOR_REG1, RTC_CNTL_DG_VDD_DRV_B_SLP, RTC_CNTL_DG_VDD_DRV_B_SLP_DEFAULT);
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// SET_PERI_REG_MASK(RTC_CNTL_DIG_REGULATOR_REG2, RTC_CNTL_REGULATOR_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_DG_WRAP_PD_EN);
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}
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if (!cfg.int_8m_pd_en) {
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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SET_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
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} else {
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_PU);
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CLEAR_PERI_REG_MASK(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_FORCE_NOGATING);
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}
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/* enable VDDSDIO control by state machine */
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REG_CLR_BIT(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_FORCE);
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REG_SET_FIELD(RTC_CNTL_SDIO_CONF_REG, RTC_CNTL_SDIO_PD_EN, cfg.vddsdio_pd_en);
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REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_DEEP_SLP_REJECT_EN, cfg.deep_slp_reject);
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REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_LIGHT_SLP_REJECT_EN, cfg.light_slp_reject);
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/* gating XTAL clock */
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REG_CLR_BIT(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_XTAL_GLOBAL_FORCE_NOGATING);
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esp_rom_uart_tx_wait_idle(0);
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}
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void rtc_sleep_low_init(uint32_t slowclk_period)
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{
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// set 5 PWC state machine times to fit in main state machine time
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_PLL_BUF_WAIT, RTC_CNTL_PLL_BUF_WAIT_SLP_CYCLES);
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_XTL_BUF_WAIT, rtc_time_us_to_slowclk(RTC_CNTL_XTL_BUF_WAIT_SLP_US, slowclk_period));
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REG_SET_FIELD(RTC_CNTL_TIMER1_REG, RTC_CNTL_CK8M_WAIT, RTC_CNTL_CK8M_WAIT_SLP_CYCLES);
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}
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void rtc_sleep_set_wakeup_time(uint64_t t)
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{
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WRITE_PERI_REG(RTC_CNTL_SLP_TIMER0_REG, t & UINT32_MAX);
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WRITE_PERI_REG(RTC_CNTL_SLP_TIMER1_REG, t >> 32);
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}
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static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu);
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uint32_t rtc_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt, uint32_t lslp_mem_inf_fpu)
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{
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REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
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REG_SET_FIELD(RTC_CNTL_SLP_REJECT_CONF_REG, RTC_CNTL_SLEEP_REJECT_ENA, reject_opt);
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/* Start entry into sleep mode */
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SET_PERI_REG_MASK(RTC_CNTL_STATE0_REG, RTC_CNTL_SLEEP_EN);
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while (GET_PERI_REG_MASK(RTC_CNTL_INT_RAW_REG,
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RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) == 0) {
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;
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}
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return rtc_sleep_finish(lslp_mem_inf_fpu);
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}
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#define STR2(X) #X
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#define STR(X) STR2(X)
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uint32_t rtc_deep_sleep_start(uint32_t wakeup_opt, uint32_t reject_opt)
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{
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REG_SET_FIELD(RTC_CNTL_WAKEUP_STATE_REG, RTC_CNTL_WAKEUP_ENA, wakeup_opt);
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WRITE_PERI_REG(RTC_CNTL_SLP_REJECT_CONF_REG, reject_opt);
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/* Calculate RTC Fast Memory CRC (for wake stub) & go to deep sleep
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Because we may be running from RTC memory as stack, we can't easily call any
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functions to do this (as registers will spill to stack, corrupting the CRC).
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Instead, load all the values we need into registers then use register ops only to calculate
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the CRC value, write it to the RTC CRC value register, and immediately go into deep sleep.
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*/
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/* Values used to set the SYSTEM_RTC_FASTMEM_CONFIG_REG value */
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const unsigned CRC_START_ADDR = 0;
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const unsigned CRC_LEN = 0x7ff;
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asm volatile(
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/* Start CRC calculation */
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"sw %1, 0(%0)\n" // set RTC_MEM_CRC_ADDR & RTC_MEM_CRC_LEN
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"or t0, %1, %2\n"
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"sw t0, 0(%0)\n" // set RTC_MEM_CRC_START
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/* Wait for the CRC calculation to finish */
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".Lwaitcrc:\n"
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"fence\n"
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"lw t0, 0(%0)\n"
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"li t1, "STR(SYSTEM_RTC_MEM_CRC_FINISH)"\n"
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"and t0, t0, t1\n"
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"beqz t0, .Lwaitcrc\n"
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"not %2, %2\n" // %2 -> ~DPORT_RTC_MEM_CRC_START
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"and t0, t0, %2\n"
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"sw t0, 0(%0)\n" // clear RTC_MEM_CRC_START
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"fence\n"
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"not %2, %2\n" // %2 -> DPORT_RTC_MEM_CRC_START, probably unnecessary but gcc assumes inputs unchanged
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/* Store the calculated value in RTC_MEM_CRC_REG */
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"lw t0, 0(%3)\n"
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"sw t0, 0(%4)\n"
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"fence\n"
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/* Set register bit to go into deep sleep */
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"lw t0, 0(%5)\n"
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"or t0, t0, %6\n"
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|
"sw t0, 0(%5)\n"
|
|
"fence\n"
|
|
|
|
/* Wait for sleep reject interrupt (never finishes if successful) */
|
|
".Lwaitsleep:"
|
|
"fence\n"
|
|
"lw t0, 0(%7)\n"
|
|
"and t0, t0, %8\n"
|
|
"beqz t0, .Lwaitsleep\n"
|
|
|
|
:
|
|
:
|
|
"r" (SYSTEM_RTC_FASTMEM_CONFIG_REG), // %0
|
|
"r" ( (CRC_START_ADDR << SYSTEM_RTC_MEM_CRC_START_S)
|
|
| (CRC_LEN << SYSTEM_RTC_MEM_CRC_LEN_S)), // %1
|
|
"r" (SYSTEM_RTC_MEM_CRC_START), // %2
|
|
"r" (SYSTEM_RTC_FASTMEM_CRC_REG), // %3
|
|
"r" (RTC_MEMORY_CRC_REG), // %4
|
|
"r" (RTC_CNTL_STATE0_REG), // %5
|
|
"r" (RTC_CNTL_SLEEP_EN), // %6
|
|
"r" (RTC_CNTL_INT_RAW_REG), // %7
|
|
"r" (RTC_CNTL_SLP_REJECT_INT_RAW | RTC_CNTL_SLP_WAKEUP_INT_RAW) // %8
|
|
: "t0", "t1" // working registers
|
|
);
|
|
|
|
return rtc_sleep_finish(0);
|
|
}
|
|
|
|
static uint32_t rtc_sleep_finish(uint32_t lslp_mem_inf_fpu)
|
|
{
|
|
/* In deep sleep mode, we never get here */
|
|
uint32_t reject = REG_GET_FIELD(RTC_CNTL_INT_RAW_REG, RTC_CNTL_SLP_REJECT_INT_RAW);
|
|
SET_PERI_REG_MASK(RTC_CNTL_INT_CLR_REG,
|
|
RTC_CNTL_SLP_REJECT_INT_CLR | RTC_CNTL_SLP_WAKEUP_INT_CLR);
|
|
|
|
/* restore config if it is a light sleep */
|
|
if (lslp_mem_inf_fpu) {
|
|
rtc_sleep_pu_config_t pu_cfg = RTC_SLEEP_PU_CONFIG_ALL(1);
|
|
rtc_sleep_pu(pu_cfg);
|
|
}
|
|
return reject;
|
|
}
|