kopia lustrzana https://github.com/espressif/esp-idf
92 wiersze
2.9 KiB
C
92 wiersze
2.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2020-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <stdint.h>
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#include <stddef.h>
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#include <stdlib.h>
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#include "sdkconfig.h"
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#include "esp32h2/rom/ets_sys.h"
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#include "esp32h2/rom/rtc.h"
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#include "esp32h2/rom/uart.h"
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#include "esp32h2/rom/gpio.h"
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#include "soc/rtc.h"
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#include "soc/rtc_periph.h"
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#include "soc/rtc_cntl_reg.h"
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#include "soc/efuse_periph.h"
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#include "soc/syscon_reg.h"
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#include "hal/cpu_hal.h"
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#include "regi2c_ctrl.h"
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#include "esp_hw_log.h"
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#include "sdkconfig.h"
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#include "rtc_clk_common.h"
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#include "esp_rom_uart.h"
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#include "soc/efuse_reg.h"
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#include "soc/syscon_reg.h"
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#include "soc/system_reg.h"
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#include "rtc_clk_common.h"
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#include "esp_rom_sys.h"
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static const char *TAG = "rtc_clk_init";
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void rtc_clk_init(rtc_clk_config_t cfg)
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{
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rtc_cpu_freq_config_t old_config, new_config;
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/* Set tuning parameters for 8M and 150k clocks.
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* Note: this doesn't attempt to set the clocks to precise frequencies.
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* Instead, we calibrate these clocks against XTAL frequency later, when necessary.
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* - SCK_DCAP value controls tuning of 150k clock.
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* The higher the value of DCAP is, the lower is the frequency.
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* - CK8M_DFREQ value controls tuning of 8M clock.
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* CLK_8M_DFREQ constant gives the best temperature characteristics.
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*/
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#if CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_2
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REG_SET_FIELD(RTC_CNTL_REGULATOR_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
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#elif CONFIG_IDF_TARGET_ESP32H2_BETA_VERSION_1
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REG_SET_FIELD(RTC_CNTL_REG, RTC_CNTL_SCK_DCAP, cfg.slow_clk_dcap);
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#endif
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REG_SET_FIELD(RTC_CNTL_CLK_CONF_REG, RTC_CNTL_CK8M_DFREQ, cfg.clk_8m_dfreq);
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/* enable modem clk */
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REG_WRITE(SYSTEM_MODEM_CLK_EN_REG, UINT32_MAX);
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/* Configure 150k clock division */
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rtc_clk_divider_set(cfg.clk_rtc_clk_div);
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/* Configure 8M clock division */
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rtc_clk_8m_divider_set(cfg.clk_8m_clk_div);
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rtc_xtal_freq_t xtal_freq = cfg.xtal_freq;
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esp_rom_uart_tx_wait_idle(0);
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rtc_clk_xtal_freq_update(xtal_freq);
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rtc_clk_apb_freq_update(rtc_clk_apb_freq_get());
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/* Set CPU frequency */
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rtc_clk_cpu_freq_get_config(&old_config);
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uint32_t freq_before = old_config.freq_mhz;
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root_clk_slt(cfg.root_clk_slt);
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bool res = rtc_clk_cpu_freq_mhz_to_config(cfg.cpu_freq_mhz, &new_config);
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if (!res) {
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ESP_HW_LOGE(TAG, "invalid CPU frequency value");
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abort();
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}
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rtc_clk_cpu_freq_set_config(&new_config);
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/* Re-calculate the ccount to make time calculation correct. */
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cpu_hal_set_cycle_count( (uint64_t)cpu_hal_get_cycle_count() * cfg.cpu_freq_mhz / freq_before );
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/* Slow & fast clocks setup */
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if (cfg.slow_freq == RTC_SLOW_FREQ_32K_XTAL) {
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rtc_clk_32k_enable(true);
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}
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if (cfg.fast_freq == RTC_FAST_FREQ_8M) {
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rtc_dig_clk8m_enable();
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}
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rtc_clk_fast_freq_set(cfg.fast_freq);
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rtc_clk_slow_freq_set(cfg.slow_freq);
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}
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