kopia lustrzana https://github.com/espressif/esp-idf
98 wiersze
2.9 KiB
C
98 wiersze
2.9 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2022 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#include "esp_attr.h"
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#include "esp_bit_defs.h"
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#include "soc/clk_tree_defs.h"
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#include "soc/soc_caps.h"
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#include "sdkconfig.h"
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief Enum with the three SPI peripherals that are software-accessible in it
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*/
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typedef enum {
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//SPI1 can be used as GPSPI only on ESP32
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SPI1_HOST=0, ///< SPI1
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SPI2_HOST=1, ///< SPI2
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#if SOC_SPI_PERIPH_NUM > 2
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SPI3_HOST=2, ///< SPI3
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#endif
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SPI_HOST_MAX, ///< invalid host value
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} spi_host_device_t;
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/**
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* @brief Type of SPI clock source.
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*/
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typedef soc_periph_spi_clk_src_t spi_clock_source_t;
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/// SPI Events
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typedef enum {
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/* Slave HD Only */
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SPI_EV_BUF_TX = BIT(0), ///< The buffer has sent data to master.
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SPI_EV_BUF_RX = BIT(1), ///< The buffer has received data from master.
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SPI_EV_SEND_DMA_READY = BIT(2), ///< Slave has loaded its TX data buffer to the hardware (DMA).
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SPI_EV_SEND = BIT(3), ///< Master has received certain number of the data, the number is determined by Master.
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SPI_EV_RECV_DMA_READY = BIT(4), ///< Slave has loaded its RX data buffer to the hardware (DMA).
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SPI_EV_RECV = BIT(5), ///< Slave has received certain number of data from master, the number is determined by Master.
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SPI_EV_CMD9 = BIT(6), ///< Received CMD9 from master.
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SPI_EV_CMDA = BIT(7), ///< Received CMDA from master.
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/* Common Event */
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SPI_EV_TRANS = BIT(8), ///< A transaction has done
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} spi_event_t;
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/**
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* @brief Line mode of SPI transaction phases: CMD, ADDR, DOUT/DIN.
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*/
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typedef struct {
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uint8_t cmd_lines; ///< The line width of command phase, e.g. 2-line-cmd-phase.
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uint8_t addr_lines; ///< The line width of address phase, e.g. 1-line-addr-phase.
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uint8_t data_lines; ///< The line width of data phase, e.g. 4-line-data-phase.
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} spi_line_mode_t;
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/**
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* @brief SPI command.
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*/
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typedef enum {
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/* Slave HD Only */
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SPI_CMD_HD_WRBUF = BIT(0),
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SPI_CMD_HD_RDBUF = BIT(1),
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SPI_CMD_HD_WRDMA = BIT(2),
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SPI_CMD_HD_RDDMA = BIT(3),
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SPI_CMD_HD_SEG_END = BIT(4),
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SPI_CMD_HD_EN_QPI = BIT(5),
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SPI_CMD_HD_WR_END = BIT(6),
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SPI_CMD_HD_INT0 = BIT(7),
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SPI_CMD_HD_INT1 = BIT(8),
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SPI_CMD_HD_INT2 = BIT(9),
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} spi_command_t;
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/** @cond */ //Doxy command to hide preprocessor definitions from docs */
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//alias for different chips, deprecated for the chips after esp32s2
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#ifdef CONFIG_IDF_TARGET_ESP32
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#define SPI_HOST SPI1_HOST
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#define HSPI_HOST SPI2_HOST
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#define VSPI_HOST SPI3_HOST
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#elif CONFIG_IDF_TARGET_ESP32S2
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// SPI_HOST (SPI1_HOST) is not supported by the SPI Master and SPI Slave driver on ESP32-S2 and later
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#define SPI_HOST SPI1_HOST
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#define FSPI_HOST SPI2_HOST
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#define HSPI_HOST SPI3_HOST
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#endif
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/** @endcond */
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#ifdef __cplusplus
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}
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#endif
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