kopia lustrzana https://github.com/espressif/esp-idf
100 wiersze
3.5 KiB
C
100 wiersze
3.5 KiB
C
/*
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* SPDX-FileCopyrightText: 2022-2023 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#ifdef __cplusplus
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extern "C" {
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#endif
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/**
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* @brief DMA block transfer type
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*/
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typedef enum {
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DW_GDMA_BLOCK_TRANSFER_CONTIGUOUS, /*!< Contiguous buffer address */
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DW_GDMA_BLOCK_TRANSFER_RELOAD, /*!< Reload transfer configuration automatically */
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DW_GDMA_BLOCK_TRANSFER_SHADOW, /*!< Shadow register */
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DW_GDMA_BLOCK_TRANSFER_LIST, /*!< Link list */
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} dw_gdma_block_transfer_type_t;
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/**
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* @brief Flow control type
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*/
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typedef enum {
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DW_GDMA_FLOW_CTRL_SELF, /*!< Flow controller is the DMA engine itself */
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DW_GDMA_FLOW_CTRL_SRC, /*!< Flow controller is the source peripheral */
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DW_GDMA_FLOW_CTRL_DST, /*!< Flow controller is the destination peripheral */
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} dw_gdma_flow_controller_t;
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/**
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* @brief Handshake interface type
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*/
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typedef enum {
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DW_GDMA_HANDSHAKE_HW, /*!< Transaction requests are initiated by hardware */
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DW_GDMA_HANDSHAKE_SW, /*!< Transaction requests are initiated by software */
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} dw_gdma_handshake_type_t;
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/**
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* @brief Role of the DMA source/destination
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*/
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typedef enum {
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DW_GDMA_ROLE_MEM, /*!< Target is a plain memory which is accessible by the DMA */
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DW_GDMA_ROLE_PERIPH_DSI, /*!< Target is FIFO memory of peripheral: DSI */
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DW_GDMA_ROLE_PERIPH_CSI, /*!< Target is FIFO memory of peripheral: CSI */
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DW_GDMA_ROLE_PERIPH_ISP, /*!< Target is FIFO memory of peripheral: ISP */
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} dw_gdma_role_t;
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/**
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* @brief Channel lock level
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*/
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typedef enum {
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DW_GDMA_LOCK_LEVEL_FULL_TRANS, /*!< Lock over complete DMA transfer */
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DW_GDMA_LOCK_LEVEL_BLOCK_TRANS, /*!< Lock over DMA block transfer */
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} dw_gdma_lock_level_t;
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/**
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* @brief DW_GDMA transfer width
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*/
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typedef enum {
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DW_GDMA_TRANS_WIDTH_8, /*!< Data transfer width: 8 bits */
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DW_GDMA_TRANS_WIDTH_16, /*!< Data transfer width: 16 bits */
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DW_GDMA_TRANS_WIDTH_32, /*!< Data transfer width: 32 bits */
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DW_GDMA_TRANS_WIDTH_64, /*!< Data transfer width: 64 bits */
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DW_GDMA_TRANS_WIDTH_128, /*!< Data transfer width: 128 bits */
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DW_GDMA_TRANS_WIDTH_256, /*!< Data transfer width: 256 bits */
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DW_GDMA_TRANS_WIDTH_512, /*!< Data transfer width: 512 bits */
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} dw_gdma_transfer_width_t;
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/**
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* @brief DW_GDMA burst mode
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*/
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typedef enum {
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DW_GDMA_BURST_MODE_INCREMENT, /*!< The address is increased after each transfer */
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DW_GDMA_BURST_MODE_FIXED, /*!< The address remains the same after each transfer */
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} dw_gdma_burst_mode_t;
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/**
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* @brief Number of data items that are contained in one burst transaction
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*
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* @note One item's bit width is set by `dw_gdma_transfer_width_t`
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*/
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typedef enum {
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DW_GDMA_BURST_ITEMS_1, /*!< 1 data items in a burst transaction */
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DW_GDMA_BURST_ITEMS_4, /*!< 4 data items in a burst transaction */
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DW_GDMA_BURST_ITEMS_8, /*!< 8 data items in a burst transaction */
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DW_GDMA_BURST_ITEMS_16, /*!< 16 data items in a burst transaction */
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DW_GDMA_BURST_ITEMS_32, /*!< 32 data items in a burst transaction */
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DW_GDMA_BURST_ITEMS_64, /*!< 64 data items in a burst transaction */
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DW_GDMA_BURST_ITEMS_128, /*!< 128 data items in a burst transaction */
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DW_GDMA_BURST_ITEMS_256, /*!< 256 data items in a burst transaction */
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DW_GDMA_BURST_ITEMS_512, /*!< 512 data items in a burst transaction */
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DW_GDMA_BURST_ITEMS_1024, /*!< 1024 data items in a burst transaction */
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} dw_gdma_burst_items_t;
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#ifdef __cplusplus
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}
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#endif
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