kopia lustrzana https://github.com/espressif/esp-idf
399 wiersze
9.4 KiB
C
399 wiersze
9.4 KiB
C
/**
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* SPDX-FileCopyrightText: 2024 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#pragma once
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#include <stdint.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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/** Group: Control/Configuration Registers */
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/** Type of mode register
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* Configures SHA algorithm
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*/
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typedef union {
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struct {
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/** mode : R/W; bitpos: [2:0]; default: 0;
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* Configures the SHA algorithm. \\
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* 0: SHA-1\\
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* 1: SHA-224\\
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* 2: SHA-256\\
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*/
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uint32_t mode:3;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} sha_mode_reg_t;
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/** Type of dma_block_num register
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* Block number register (only effective for DMA-SHA)
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*/
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typedef union {
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struct {
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/** dma_block_num : R/W; bitpos: [5:0]; default: 0;
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* Configures the DMA-SHA block number.
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*/
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uint32_t dma_block_num:6;
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uint32_t reserved_6:26;
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};
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uint32_t val;
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} sha_dma_block_num_reg_t;
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/** Type of start register
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* Starts the SHA accelerator for Typical SHA operation
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*/
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typedef union {
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struct {
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uint32_t reserved_0:1;
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/** start : RO; bitpos: [31:1]; default: 0;
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* Write 1 to start Typical SHA calculation.
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*/
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uint32_t start:31;
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};
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uint32_t val;
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} sha_start_reg_t;
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/** Type of continue register
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* Continues SHA operation (only effective in Typical SHA mode)
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*/
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typedef union {
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struct {
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uint32_t reserved_0:1;
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/** continue : RO; bitpos: [31:1]; default: 0;
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* Write 1 to continue Typical SHA calculation.
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*/
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uint32_t conti:31;
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};
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uint32_t val;
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} sha_continue_reg_t;
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/** Type of dma_start register
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* Starts the SHA accelerator for DMA-SHA operation
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*/
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typedef union {
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struct {
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/** dma_start : WO; bitpos: [0]; default: 0;
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* Write 1 to start DMA-SHA calculation.
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*/
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uint32_t dma_start:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_dma_start_reg_t;
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/** Type of dma_continue register
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* Continues SHA operation (only effective in DMA-SHA mode)
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*/
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typedef union {
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struct {
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/** dma_continue : WO; bitpos: [0]; default: 0;
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* Write 1 to continue DMA-SHA calculation.
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*/
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uint32_t dma_continue:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_dma_continue_reg_t;
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/** Group: Configuration Register */
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/** Type of t_string register
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* SHA 512/t configuration register 0.
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*/
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typedef union {
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struct {
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/** t_string : R/W; bitpos: [31:0]; default: 0;
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* Sha t_string (used if and only if mode == SHA_512/t).
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*/
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uint32_t t_string:32;
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};
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uint32_t val;
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} sha_t_string_reg_t;
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/** Type of t_length register
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* SHA 512/t configuration register 1.
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*/
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typedef union {
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struct {
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/** t_length : R/W; bitpos: [5:0]; default: 0;
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* Sha t_length (used if and only if mode == SHA_512/t).
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*/
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uint32_t t_length:6;
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uint32_t reserved_6:26;
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};
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uint32_t val;
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} sha_t_length_reg_t;
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/** Type of mode_3 register
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* Initial configuration register 0.
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*/
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typedef union {
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struct {
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/** mode_3 : R/W; bitpos: [2:0]; default: 0;
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* Sha3 mode
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*/
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uint32_t mode_3:3;
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uint32_t reserved_3:29;
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};
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uint32_t val;
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} sha_3_mode_reg_t;
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/** Type of clean_m_3 register
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* Initial configuration register 1.
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*/
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typedef union {
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struct {
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/** clean_m_3 : WO; bitpos: [0]; default: 0;
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* Clean Message.
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*/
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uint32_t clean_m_3:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_clean_m_reg_t;
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/** Type of dma_block_num_3 register
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* DMA configuration register 0.
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*/
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typedef union {
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struct {
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/** dma_block_num_3 : R/W; bitpos: [5:0]; default: 0;
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* DMA-SHA3 block number.
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*/
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uint32_t dma_block_num_3:6;
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uint32_t reserved_6:26;
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};
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uint32_t val;
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} sha_3_dma_block_num_reg_t;
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/** Type of start_3 register
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* Typical SHA3 configuration register 0.
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*/
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typedef union {
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struct {
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/** start_3 : WO; bitpos: [0]; default: 0;
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* Start typical sha3.
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*/
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uint32_t start_3:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_start_reg_t;
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/** Type of continue_3 register
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* Typical SHA3 configuration register 1.
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*/
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typedef union {
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struct {
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/** continue_3 : WO; bitpos: [0]; default: 0;
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* Continue typical sha3.
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*/
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uint32_t continue_3:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_continue_reg_t;
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/** Type of dma_start_3 register
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* DMA configuration register 1.
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*/
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typedef union {
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struct {
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/** dma_start_3 : WO; bitpos: [0]; default: 0;
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* Start dma-sha3.
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*/
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uint32_t dma_start_3:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_dma_start_reg_t;
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/** Type of dma_continue_3 register
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* DMA configuration register 2.
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*/
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typedef union {
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struct {
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/** dma_continue_3 : WO; bitpos: [0]; default: 0;
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* Continue dma-sha3.
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*/
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uint32_t dma_continue_3:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_dma_continue_reg_t;
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/** Type of shake_length_3 register
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* DMA configuration register 3.
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*/
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typedef union {
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struct {
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/** shake_length_3 : WO; bitpos: [10:0]; default: 50;
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* SHAKE output hash word length
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*/
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uint32_t shake_length_3:11;
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uint32_t reserved_11:21;
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};
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uint32_t val;
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} sha_3_shake_length_reg_t;
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/** Group: Status Registers */
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/** Type of busy register
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* Represents if SHA Accelerator is busy or not
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*/
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typedef union {
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struct {
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/** busy_state : RO; bitpos: [0]; default: 0;
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* Represents the states of SHA accelerator. \\
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* 0: idle\\
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* 1: busy\\
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*/
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uint32_t busy_state:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_busy_reg_t;
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/** Group: Interrupt Registers */
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/** Type of clear_irq register
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* DMA-SHA interrupt clear register
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*/
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typedef union {
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struct {
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/** clear_interrupt : WO; bitpos: [0]; default: 0;
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* Write 1 to clear DMA-SHA interrupt.
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*/
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uint32_t clear_interrupt:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_clear_irq_reg_t;
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/** Type of irq_ena register
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* DMA-SHA interrupt enable register
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*/
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typedef union {
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struct {
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/** interrupt_ena : R/W; bitpos: [0]; default: 0;
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* Write 1 to enable DMA-SHA interrupt.
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*/
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uint32_t interrupt_ena:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_irq_ena_reg_t;
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/** Group: Version Register */
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/** Type of date register
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* Version control register
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*/
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typedef union {
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struct {
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/** date : R/W; bitpos: [29:0]; default: 538972713;
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* Version control register.
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*/
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uint32_t date:30;
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uint32_t reserved_30:2;
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};
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uint32_t val;
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} sha_date_reg_t;
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/** Group: memory type */
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/** Group: Status Register */
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/** Type of busy_3 register
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* Busy register.
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*/
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typedef union {
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struct {
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/** busy_reg_3 : RO; bitpos: [0]; default: 0;
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* Sha3 busy state. 1'b0: idle. 1'b1: busy.
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*/
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uint32_t busy_reg_3:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_busy_reg_t;
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/** Group: Interrupt Register */
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/** Type of clear_int_3 register
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* Interrupt clear register.
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*/
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typedef union {
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struct {
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/** clear_int_3 : WO; bitpos: [0]; default: 0;
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* Clear sha3 interrupt.
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*/
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uint32_t clear_int_3:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_clear_int_reg_t;
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/** Type of int_ena_3 register
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* Interrupt enable register.
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*/
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typedef union {
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struct {
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/** int_ena_3 : R/W; bitpos: [0]; default: 0;
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* Sha3 interrupt enable register. 1'b0: disable(default). 1'b1:enable
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*/
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uint32_t int_ena_3:1;
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uint32_t reserved_1:31;
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};
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uint32_t val;
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} sha_3_int_ena_reg_t;
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typedef struct {
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volatile sha_mode_reg_t mode;
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volatile sha_t_string_reg_t t_string;
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volatile sha_t_length_reg_t t_length;
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volatile sha_dma_block_num_reg_t dma_block_num;
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volatile sha_start_reg_t start;
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volatile sha_continue_reg_t conti;
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volatile sha_busy_reg_t busy;
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volatile sha_dma_start_reg_t dma_start;
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volatile sha_dma_continue_reg_t dma_continue;
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volatile sha_clear_irq_reg_t clear_irq;
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volatile sha_irq_ena_reg_t irq_ena;
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volatile sha_date_reg_t date;
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uint32_t reserved_030[4];
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volatile uint32_t h[16];
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volatile uint32_t m[16];
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uint32_t reserved_0c0[464];
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volatile sha_3_mode_reg_t mode_3;
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volatile sha_3_clean_m_reg_t clean_m_3;
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uint32_t reserved_808;
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volatile sha_3_dma_block_num_reg_t dma_block_num_3;
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volatile sha_3_start_reg_t start_3;
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volatile sha_3_continue_reg_t continue_3;
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volatile sha_3_busy_reg_t busy_3;
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volatile sha_3_dma_start_reg_t dma_start_3;
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volatile sha_3_dma_continue_reg_t dma_continue_3;
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volatile sha_3_clear_int_reg_t clear_int_3;
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volatile sha_3_int_ena_reg_t int_ena_3;
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volatile sha_3_shake_length_reg_t shake_length_3;
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uint32_t reserved_830[52];
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volatile uint32_t m_out_3[50];
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uint32_t reserved_9c8[14];
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volatile uint32_t m_3[50];
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} sha_dev_t;
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extern sha_dev_t SHA;
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#ifndef __cplusplus
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_Static_assert(sizeof(sha_dev_t) == 0xac8, "Invalid size of sha_dev_t structure");
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#endif
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#ifdef __cplusplus
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}
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#endif
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