esp-idf/components/soc/esp32
Ivan Grokhotkov 964f5a91f7 bootloader, esp32: add workaround for Tensilica erratum 572
If zero-overhead loop buffer is enabled, under certain rare conditions
when executing a zero-overhead loop, the CPU may attempt to execute an invalid instruction. Work around by disabling the buffer.
2018-11-19 04:39:35 +00:00
..
include/soc bootloader, esp32: add workaround for Tensilica erratum 572 2018-11-19 04:39:35 +00:00
test
component.mk
cpu_util.c
gpio_periph.c
i2c_apll.h
i2c_bbpll.h
i2c_rtc_clk.h
rtc_clk.c rtc_clk: bugfix: incorrect divider setting in rtc_clk_cpu_freq_to_config() 2018-11-08 15:57:10 +05:30
rtc_clk_common.h
rtc_clk_init.c soc,sdmmc: fix build failures when NDEBUG is used 2018-10-15 14:57:12 +08:00
rtc_init.c
rtc_periph.c
rtc_pm.c
rtc_sleep.c
rtc_time.c soc,sdmmc: fix build failures when NDEBUG is used 2018-10-15 14:57:12 +08:00
rtc_wdt.c
sdio_slave_periph.c
sdmmc_periph.c
soc_log.h soc: use _EARLY versions of ESP_LOG 2018-10-15 14:59:46 +08:00
soc_memory_layout.c test: fix the unit test fail issue under single_core config 2018-10-31 17:04:32 +08:00
sources.cmake cmake: Add support for test build 2018-10-20 12:07:24 +08:00
spi_periph.c