Angus Gratton 4b4cd7fb51 efuse/flash encryption: Reduce FLASH_CRYPT_CNT to a 7 bit efuse field ... 8th bit is not used by hardware. As reported https://esp32.com/viewtopic.php?f=2&t=7800&p=40895#p40894		2019-04-03 14:07:20 +11:00
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include/soc	efuse/flash encryption: Reduce FLASH_CRYPT_CNT to a 7 bit efuse field	2019-04-03 14:07:20 +11:00
test	separate rom from esp32 component to esp_rom	2019-03-21 18:51:45 +08:00
component.mk	…
cpu_util.c	…
gpio_periph.c	…
i2c_apll.h	…
i2c_bbpll.h	…
i2c_rtc_clk.h	…
rtc_clk.c	separate rom from esp32 component to esp_rom	2019-03-21 18:51:45 +08:00
rtc_clk_common.h	…
rtc_clk_init.c	separate rom from esp32 component to esp_rom	2019-03-21 18:51:45 +08:00
rtc_init.c	…
rtc_periph.c	…
rtc_pm.c	…
rtc_sleep.c	separate rom from esp32 component to esp_rom	2019-03-21 18:51:45 +08:00
rtc_time.c	separate rom from esp32 component to esp_rom	2019-03-21 18:51:45 +08:00
rtc_wdt.c	…
sdio_slave_periph.c	…
sdmmc_periph.c	…
soc_log.h	separate rom from esp32 component to esp_rom	2019-03-21 18:51:45 +08:00
soc_memory_layout.c	…
sources.cmake	…
spi_periph.c	…