kopia lustrzana https://github.com/espressif/esp-idf
771 wiersze
25 KiB
C
771 wiersze
25 KiB
C
/*
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* SPDX-FileCopyrightText: 2015-2021 Espressif Systems (Shanghai) CO LTD
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <stdbool.h>
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#include <stddef.h>
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#include <sys/param.h>
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#include "esp_log.h"
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#include "esp_intr_alloc.h"
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#include "soc/soc_caps.h"
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#include "soc/soc_pins.h"
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#include "soc/gpio_periph.h"
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#include "esp_rom_gpio.h"
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#include "esp_rom_sys.h"
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#include "driver/gpio.h"
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#include "driver/sdmmc_host.h"
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#include "esp_private/periph_ctrl.h"
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#include "sdmmc_private.h"
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#include "freertos/FreeRTOS.h"
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#include "freertos/semphr.h"
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#include "soc/sdmmc_periph.h"
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#include "hal/gpio_hal.h"
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#define SDMMC_EVENT_QUEUE_LENGTH 32
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static void sdmmc_isr(void* arg);
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static void sdmmc_host_dma_init(void);
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static const char* TAG = "sdmmc_periph";
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static intr_handle_t s_intr_handle;
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static QueueHandle_t s_event_queue;
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static SemaphoreHandle_t s_io_intr_event;
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static size_t s_slot_width[2] = {1, 1};
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/* The following definitions are used to simplify GPIO configuration in the driver,
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* whether IOMUX or GPIO Matrix is used by the chip.
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* Two simple "APIs" are provided to the driver code:
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* - configure_pin(name, slot, mode): Configures signal "name" for the given slot and mode.
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* - GPIO_NUM(slot, name): Returns the GPIO number of signal "name" for the given slot.
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*
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* To make this work, configure_pin is defined as a macro that picks the parameters required
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* for configuring GPIO matrix or IOMUX from relevant arrays, and passes them to either of
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* configure_pin_gpio_matrix, configure_pin_iomux functions.
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* Likewise, GPIO_NUM is a macro that picks the pin number from one of the two structures.
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*
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* Macros are used rather than inline functions to look up members of different structures
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* with same names. E.g. the number of pin d3 is obtained either from .d3 member of
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* sdmmc_slot_gpio_num array (for IOMUX) or from .d3 member of s_sdmmc_slot_gpio_num array
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* (for GPIO matrix).
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*/
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#ifdef SOC_SDMMC_USE_GPIO_MATRIX
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static void configure_pin_gpio_matrix(uint8_t gpio_num, uint8_t gpio_matrix_sig, gpio_mode_t mode, const char* name);
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#define configure_pin(name, slot, mode) \
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configure_pin_gpio_matrix(s_sdmmc_slot_gpio_num[slot].name, sdmmc_slot_gpio_sig[slot].name, mode, #name)
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static sdmmc_slot_io_info_t s_sdmmc_slot_gpio_num[SOC_SDMMC_NUM_SLOTS];
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#define GPIO_NUM(slot, name) s_sdmmc_slot_gpio_num[slot].name
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#elif SOC_SDMMC_USE_IOMUX
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static void configure_pin_iomux(uint8_t gpio_num);
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#define configure_pin(name, slot, mode) configure_pin_iomux(sdmmc_slot_gpio_num[slot].name)
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#define GPIO_NUM(slot, name) sdmmc_slot_gpio_num[slot].name
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#endif // SOC_SDMMC_USE_GPIO_MATRIX
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static esp_err_t sdmmc_host_pullup_en_internal(int slot, int width);
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void sdmmc_host_reset(void)
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{
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// Set reset bits
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SDMMC.ctrl.controller_reset = 1;
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SDMMC.ctrl.dma_reset = 1;
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SDMMC.ctrl.fifo_reset = 1;
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// Wait for the reset bits to be cleared by hardware
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while (SDMMC.ctrl.controller_reset || SDMMC.ctrl.fifo_reset || SDMMC.ctrl.dma_reset) {
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;
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}
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}
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/* We have two clock divider stages:
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* - one is the clock generator which drives SDMMC peripheral,
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* it can be configured using SDMMC.clock register. It can generate
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* frequencies 160MHz/(N + 1), where 0 < N < 16, I.e. from 10 to 80 MHz.
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* - 4 clock dividers inside SDMMC peripheral, which can divide clock
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* from the first stage by 2 * M, where 0 < M < 255
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* (they can also be bypassed).
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*
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* For cards which aren't UHS-1 or UHS-2 cards, which we don't support,
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* maximum bus frequency in high speed (HS) mode is 50 MHz.
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* Note: for non-UHS-1 cards, HS mode is optional.
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* Default speed (DS) mode is mandatory, it works up to 25 MHz.
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* Whether the card supports HS or not can be determined using TRAN_SPEED
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* field of card's CSD register.
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*
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* 50 MHz can not be obtained exactly, closest we can get is 53 MHz.
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*
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* The first stage divider is set to the highest possible value for the given
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* frequency, and the the second stage dividers are used if division factor
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* is >16.
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*
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* Of the second stage dividers, div0 is used for card 0, and div1 is used
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* for card 1.
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*/
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static void sdmmc_host_set_clk_div(int div)
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{
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// Set frequency to 160MHz / div
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// div = p + 1
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// duty cycle = (h + 1)/(p + 1) (should be = 1/2)
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assert (div > 1 && div <= 16);
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int p = div - 1;
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int h = div / 2 - 1;
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SDMMC.clock.div_factor_p = p;
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SDMMC.clock.div_factor_h = h;
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SDMMC.clock.div_factor_m = p;
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// Make sure 160 MHz source clock is used
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#if SOC_SDMMC_SUPPORT_XTAL_CLOCK
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SDMMC.clock.clk_sel = 1;
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#endif
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#if SOC_SDMMC_USE_GPIO_MATRIX
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// 90 degree phase on input and output clocks
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const int inout_clock_phase = 1;
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#else
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// 180 degree phase on input and output clocks
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const int inout_clock_phase = 4;
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#endif
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// Set phases for in/out clocks
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SDMMC.clock.phase_dout = inout_clock_phase;
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SDMMC.clock.phase_din = inout_clock_phase;
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SDMMC.clock.phase_core = 0;
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// Wait for the clock to propagate
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esp_rom_delay_us(10);
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}
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static void sdmmc_host_input_clk_disable(void)
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{
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SDMMC.clock.val = 0;
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}
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static void sdmmc_host_clock_update_command(int slot)
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{
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// Clock update command (not a real command; just updates CIU registers)
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sdmmc_hw_cmd_t cmd_val = {
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.card_num = slot,
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.update_clk_reg = 1,
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.wait_complete = 1
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};
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bool repeat = true;
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while(repeat) {
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sdmmc_host_start_command(slot, cmd_val, 0);
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while (true) {
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// Sending clock update command to the CIU can generate HLE error.
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// According to the manual, this is okay and we must retry the command.
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if (SDMMC.rintsts.hle) {
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SDMMC.rintsts.hle = 1;
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repeat = true;
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break;
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}
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// When the command is accepted by CIU, start_command bit will be
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// cleared in SDMMC.cmd register.
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if (SDMMC.cmd.start_command == 0) {
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repeat = false;
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break;
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}
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}
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}
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}
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void sdmmc_host_get_clk_dividers(const uint32_t freq_khz, int *host_div, int *card_div)
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{
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// Calculate new dividers
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if (freq_khz >= SDMMC_FREQ_HIGHSPEED) {
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*host_div = 4; // 160 MHz / 4 = 40 MHz
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*card_div = 0;
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} else if (freq_khz == SDMMC_FREQ_DEFAULT) {
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*host_div = 8; // 160 MHz / 8 = 20 MHz
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*card_div = 0;
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} else if (freq_khz == SDMMC_FREQ_PROBING) {
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*host_div = 10; // 160 MHz / 10 / (20 * 2) = 400 kHz
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*card_div = 20;
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} else {
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/*
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* for custom frequencies use maximum range of host divider (1-16), find the closest <= div. combination
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* if exceeded, combine with the card divider to keep reasonable precision (applies mainly to low frequencies)
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* effective frequency range: 400 kHz - 32 MHz (32.1 - 39.9 MHz cannot be covered with given divider scheme)
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*/
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*host_div = (2 * APB_CLK_FREQ) / (freq_khz * 1000);
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if (*host_div > 15 ) {
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*host_div = 2;
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*card_div = APB_CLK_FREQ / (2 * freq_khz * 1000);
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if ( (APB_CLK_FREQ % (2 * freq_khz * 1000)) > 0 ) {
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(*card_div)++;
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}
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} else if ( ((2 * APB_CLK_FREQ) % (freq_khz * 1000)) > 0 ) {
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(*host_div)++;
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}
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}
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}
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static int sdmmc_host_calc_freq(const int host_div, const int card_div)
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{
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return 2 * APB_CLK_FREQ / host_div / ((card_div == 0) ? 1 : card_div * 2) / 1000;
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}
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esp_err_t sdmmc_host_set_card_clk(int slot, uint32_t freq_khz)
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{
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if (!(slot == 0 || slot == 1)) {
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return ESP_ERR_INVALID_ARG;
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}
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// Disable clock first
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SDMMC.clkena.cclk_enable &= ~BIT(slot);
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sdmmc_host_clock_update_command(slot);
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int host_div = 0; /* clock divider of the host (SDMMC.clock) */
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int card_div = 0; /* 1/2 of card clock divider (SDMMC.clkdiv) */
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sdmmc_host_get_clk_dividers(freq_khz, &host_div, &card_div);
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int real_freq = sdmmc_host_calc_freq(host_div, card_div);
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ESP_LOGD(TAG, "slot=%d host_div=%d card_div=%d freq=%dkHz (max %" PRIu32 "kHz)", slot, host_div, card_div, real_freq, freq_khz);
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// Program CLKDIV and CLKSRC, send them to the CIU
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switch(slot) {
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case 0:
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SDMMC.clksrc.card0 = 0;
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SDMMC.clkdiv.div0 = card_div;
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break;
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case 1:
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SDMMC.clksrc.card1 = 1;
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SDMMC.clkdiv.div1 = card_div;
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break;
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}
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sdmmc_host_set_clk_div(host_div);
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sdmmc_host_clock_update_command(slot);
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// Re-enable clocks
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SDMMC.clkena.cclk_enable |= BIT(slot);
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SDMMC.clkena.cclk_low_power |= BIT(slot);
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sdmmc_host_clock_update_command(slot);
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// set data timeout
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const uint32_t data_timeout_ms = 100;
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uint32_t data_timeout_cycles = data_timeout_ms * freq_khz;
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const uint32_t data_timeout_cycles_max = 0xffffff;
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if (data_timeout_cycles > data_timeout_cycles_max) {
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data_timeout_cycles = data_timeout_cycles_max;
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}
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SDMMC.tmout.data = data_timeout_cycles;
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// always set response timeout to highest value, it's small enough anyway
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SDMMC.tmout.response = 255;
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return ESP_OK;
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}
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esp_err_t sdmmc_host_get_real_freq(int slot, int* real_freq_khz)
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{
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if (real_freq_khz == NULL) {
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return ESP_ERR_INVALID_ARG;
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}
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if (!(slot == 0 || slot == 1)) {
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return ESP_ERR_INVALID_ARG;
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}
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int host_div = SDMMC.clock.div_factor_p + 1;
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int card_div = slot == 0 ? SDMMC.clkdiv.div0 : SDMMC.clkdiv.div1;
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*real_freq_khz = sdmmc_host_calc_freq(host_div, card_div);
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return ESP_OK;
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}
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esp_err_t sdmmc_host_start_command(int slot, sdmmc_hw_cmd_t cmd, uint32_t arg) {
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if (!(slot == 0 || slot == 1)) {
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return ESP_ERR_INVALID_ARG;
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}
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if ((SDMMC.cdetect.cards & BIT(slot)) != 0) {
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return ESP_ERR_NOT_FOUND;
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}
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if (cmd.data_expected && cmd.rw && (SDMMC.wrtprt.cards & BIT(slot)) != 0) {
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return ESP_ERR_INVALID_STATE;
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}
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while (SDMMC.cmd.start_command == 1) {
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;
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}
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SDMMC.cmdarg = arg;
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cmd.card_num = slot;
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cmd.start_command = 1;
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SDMMC.cmd = cmd;
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return ESP_OK;
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}
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esp_err_t sdmmc_host_init(void)
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{
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if (s_intr_handle) {
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return ESP_ERR_INVALID_STATE;
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}
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periph_module_reset(PERIPH_SDMMC_MODULE);
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periph_module_enable(PERIPH_SDMMC_MODULE);
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// Enable clock to peripheral. Use smallest divider first.
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sdmmc_host_set_clk_div(2);
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// Reset
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sdmmc_host_reset();
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ESP_LOGD(TAG, "peripheral version %"PRIx32", hardware config %08"PRIx32, SDMMC.verid, SDMMC.hcon);
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// Clear interrupt status and set interrupt mask to known state
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SDMMC.rintsts.val = 0xffffffff;
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SDMMC.intmask.val = 0;
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SDMMC.ctrl.int_enable = 0;
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// Allocate event queue
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s_event_queue = xQueueCreate(SDMMC_EVENT_QUEUE_LENGTH, sizeof(sdmmc_event_t));
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if (!s_event_queue) {
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return ESP_ERR_NO_MEM;
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}
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s_io_intr_event = xSemaphoreCreateBinary();
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if (!s_io_intr_event) {
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vQueueDelete(s_event_queue);
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s_event_queue = NULL;
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return ESP_ERR_NO_MEM;
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}
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// Attach interrupt handler
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esp_err_t ret = esp_intr_alloc(ETS_SDIO_HOST_INTR_SOURCE, 0, &sdmmc_isr, s_event_queue, &s_intr_handle);
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if (ret != ESP_OK) {
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vQueueDelete(s_event_queue);
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s_event_queue = NULL;
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vSemaphoreDelete(s_io_intr_event);
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s_io_intr_event = NULL;
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return ret;
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}
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// Enable interrupts
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SDMMC.intmask.val =
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SDMMC_INTMASK_CD |
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SDMMC_INTMASK_CMD_DONE |
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SDMMC_INTMASK_DATA_OVER |
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SDMMC_INTMASK_RCRC | SDMMC_INTMASK_DCRC |
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SDMMC_INTMASK_RTO | SDMMC_INTMASK_DTO | SDMMC_INTMASK_HTO |
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SDMMC_INTMASK_SBE | SDMMC_INTMASK_EBE |
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SDMMC_INTMASK_RESP_ERR | SDMMC_INTMASK_HLE; //sdio is enabled only when use.
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SDMMC.ctrl.int_enable = 1;
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// Disable generation of Busy Clear Interrupt
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SDMMC.cardthrctl.busy_clr_int_en = 0;
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// Enable DMA
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sdmmc_host_dma_init();
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// Initialize transaction handler
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ret = sdmmc_host_transaction_handler_init();
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if (ret != ESP_OK) {
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vQueueDelete(s_event_queue);
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s_event_queue = NULL;
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vSemaphoreDelete(s_io_intr_event);
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s_io_intr_event = NULL;
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esp_intr_free(s_intr_handle);
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s_intr_handle = NULL;
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return ret;
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}
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return ESP_OK;
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}
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#ifdef SOC_SDMMC_USE_IOMUX
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static void configure_pin_iomux(uint8_t gpio_num)
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{
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const int sdmmc_func = 3;
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const int drive_strength = 3;
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assert(gpio_num != (uint8_t) GPIO_NUM_NC);
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gpio_pulldown_dis(gpio_num);
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uint32_t reg = GPIO_PIN_MUX_REG[gpio_num];
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assert(reg != UINT32_MAX);
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PIN_INPUT_ENABLE(reg);
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gpio_hal_iomux_func_sel(reg, sdmmc_func);
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PIN_SET_DRV(reg, drive_strength);
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}
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#elif SOC_SDMMC_USE_GPIO_MATRIX
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static void configure_pin_gpio_matrix(uint8_t gpio_num, uint8_t gpio_matrix_sig, gpio_mode_t mode, const char* name)
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{
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assert (gpio_num != (uint8_t) GPIO_NUM_NC);
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ESP_LOGD(TAG, "using GPIO%d as %s pin", gpio_num, name);
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gpio_reset_pin(gpio_num);
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gpio_set_direction(gpio_num, mode);
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gpio_pulldown_dis(gpio_num);
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if (mode == GPIO_MODE_INPUT || mode == GPIO_MODE_INPUT_OUTPUT) {
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esp_rom_gpio_connect_in_signal(gpio_num, gpio_matrix_sig, false);
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}
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if (mode == GPIO_MODE_OUTPUT || mode == GPIO_MODE_INPUT_OUTPUT) {
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esp_rom_gpio_connect_out_signal(gpio_num, gpio_matrix_sig, false, false);
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}
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}
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#endif // SOC_SDMMC_USE_{IOMUX,GPIO_MATRIX}
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esp_err_t sdmmc_host_init_slot(int slot, const sdmmc_slot_config_t* slot_config)
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{
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if (!s_intr_handle) {
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return ESP_ERR_INVALID_STATE;
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}
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if (!(slot == 0 || slot == 1)) {
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return ESP_ERR_INVALID_ARG;
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}
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if (slot_config == NULL) {
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return ESP_ERR_INVALID_ARG;
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}
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int gpio_cd = slot_config->cd;
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int gpio_wp = slot_config->wp;
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uint8_t slot_width = slot_config->width;
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// Configure pins
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const sdmmc_slot_info_t* slot_info = &sdmmc_slot_info[slot];
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if (slot_width == SDMMC_SLOT_WIDTH_DEFAULT) {
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slot_width = slot_info->width;
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}
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else if (slot_width > slot_info->width) {
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return ESP_ERR_INVALID_ARG;
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}
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s_slot_width[slot] = slot_width;
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#if SOC_SDMMC_USE_GPIO_MATRIX
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/* Save pin configuration for this slot */
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s_sdmmc_slot_gpio_num[slot].clk = slot_config->clk;
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s_sdmmc_slot_gpio_num[slot].cmd = slot_config->cmd;
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s_sdmmc_slot_gpio_num[slot].d0 = slot_config->d0;
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/* Save d1 even in 1-line mode, it might be needed for SDIO INT line */
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s_sdmmc_slot_gpio_num[slot].d1 = slot_config->d1;
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if (slot_width >= 4) {
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s_sdmmc_slot_gpio_num[slot].d2 = slot_config->d2;
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}
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/* Save d3 even for 1-line mode, as it needs to be set high */
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s_sdmmc_slot_gpio_num[slot].d3 = slot_config->d3;
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if (slot_width >= 8) {
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s_sdmmc_slot_gpio_num[slot].d4 = slot_config->d4;
|
|
s_sdmmc_slot_gpio_num[slot].d5 = slot_config->d5;
|
|
s_sdmmc_slot_gpio_num[slot].d6 = slot_config->d6;
|
|
s_sdmmc_slot_gpio_num[slot].d7 = slot_config->d7;
|
|
}
|
|
#endif
|
|
|
|
bool pullup = slot_config->flags & SDMMC_SLOT_FLAG_INTERNAL_PULLUP;
|
|
if (pullup) {
|
|
sdmmc_host_pullup_en_internal(slot, slot_config->width);
|
|
}
|
|
|
|
configure_pin(clk, slot, GPIO_MODE_OUTPUT);
|
|
configure_pin(cmd, slot, GPIO_MODE_INPUT_OUTPUT);
|
|
configure_pin(d0, slot, GPIO_MODE_INPUT_OUTPUT);
|
|
|
|
if (slot_width >= 4) {
|
|
configure_pin(d1, slot, GPIO_MODE_INPUT_OUTPUT);
|
|
configure_pin(d2, slot, GPIO_MODE_INPUT_OUTPUT);
|
|
// Force D3 high to make slave enter SD mode.
|
|
// Connect to peripheral after width configuration.
|
|
gpio_config_t gpio_conf = {
|
|
.pin_bit_mask = BIT64(GPIO_NUM(slot, d3)),
|
|
.mode = GPIO_MODE_OUTPUT,
|
|
.pull_up_en = 0,
|
|
.pull_down_en = 0,
|
|
.intr_type = GPIO_INTR_DISABLE,
|
|
};
|
|
gpio_config(&gpio_conf);
|
|
gpio_set_level(GPIO_NUM(slot, d3), 1);
|
|
}
|
|
if (slot_width == 8) {
|
|
configure_pin(d4, slot, GPIO_MODE_INPUT_OUTPUT);
|
|
configure_pin(d5, slot, GPIO_MODE_INPUT_OUTPUT);
|
|
configure_pin(d6, slot, GPIO_MODE_INPUT_OUTPUT);
|
|
configure_pin(d7, slot, GPIO_MODE_INPUT_OUTPUT);
|
|
}
|
|
|
|
// SDIO slave interrupt is edge sensitive to ~(int_n | card_int | card_detect)
|
|
// set this and card_detect to high to enable sdio interrupt
|
|
esp_rom_gpio_connect_in_signal(GPIO_MATRIX_CONST_ONE_INPUT, slot_info->card_int, false);
|
|
|
|
// Set up Card Detect input
|
|
int matrix_in_cd;
|
|
if (gpio_cd != SDMMC_SLOT_NO_CD) {
|
|
ESP_LOGD(TAG, "using GPIO%d as CD pin", gpio_cd);
|
|
esp_rom_gpio_pad_select_gpio(gpio_cd);
|
|
gpio_set_direction(gpio_cd, GPIO_MODE_INPUT);
|
|
matrix_in_cd = gpio_cd;
|
|
} else {
|
|
// if not set, default to CD low (card present)
|
|
matrix_in_cd = GPIO_MATRIX_CONST_ZERO_INPUT;
|
|
}
|
|
esp_rom_gpio_connect_in_signal(matrix_in_cd, slot_info->card_detect, false);
|
|
|
|
// Set up Write Protect input
|
|
int matrix_in_wp;
|
|
if (gpio_wp != SDMMC_SLOT_NO_WP) {
|
|
ESP_LOGD(TAG, "using GPIO%d as WP pin", gpio_wp);
|
|
esp_rom_gpio_pad_select_gpio(gpio_wp);
|
|
gpio_set_direction(gpio_wp, GPIO_MODE_INPUT);
|
|
matrix_in_wp = gpio_wp;
|
|
} else {
|
|
// if not set, default to WP high (not write protected)
|
|
matrix_in_wp = GPIO_MATRIX_CONST_ONE_INPUT;
|
|
}
|
|
// WP signal is normally active low, but hardware expects
|
|
// an active-high signal, so invert it in GPIO matrix
|
|
esp_rom_gpio_connect_in_signal(matrix_in_wp, slot_info->write_protect, true);
|
|
|
|
// By default, set probing frequency (400kHz) and 1-bit bus
|
|
esp_err_t ret = sdmmc_host_set_card_clk(slot, 400);
|
|
if (ret != ESP_OK) {
|
|
return ret;
|
|
}
|
|
ret = sdmmc_host_set_bus_width(slot, 1);
|
|
if (ret != ESP_OK) {
|
|
return ret;
|
|
}
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t sdmmc_host_deinit(void)
|
|
{
|
|
if (!s_intr_handle) {
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
esp_intr_free(s_intr_handle);
|
|
s_intr_handle = NULL;
|
|
vQueueDelete(s_event_queue);
|
|
s_event_queue = NULL;
|
|
vQueueDelete(s_io_intr_event);
|
|
s_io_intr_event = NULL;
|
|
sdmmc_host_input_clk_disable();
|
|
sdmmc_host_transaction_handler_deinit();
|
|
periph_module_disable(PERIPH_SDMMC_MODULE);
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t sdmmc_host_wait_for_event(int tick_count, sdmmc_event_t* out_event)
|
|
{
|
|
if (!out_event) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
if (!s_event_queue) {
|
|
return ESP_ERR_INVALID_STATE;
|
|
}
|
|
int ret = xQueueReceive(s_event_queue, out_event, tick_count);
|
|
if (ret == pdFALSE) {
|
|
return ESP_ERR_TIMEOUT;
|
|
}
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t sdmmc_host_set_bus_width(int slot, size_t width)
|
|
{
|
|
if (!(slot == 0 || slot == 1)) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
if (sdmmc_slot_info[slot].width < width) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
const uint16_t mask = BIT(slot);
|
|
if (width == 1) {
|
|
SDMMC.ctype.card_width_8 &= ~mask;
|
|
SDMMC.ctype.card_width &= ~mask;
|
|
} else if (width == 4) {
|
|
SDMMC.ctype.card_width_8 &= ~mask;
|
|
SDMMC.ctype.card_width |= mask;
|
|
// D3 was set to GPIO high to force slave into SD mode, until 4-bit mode is set
|
|
configure_pin(d3, slot, GPIO_MODE_INPUT_OUTPUT);
|
|
} else if (width == 8) {
|
|
SDMMC.ctype.card_width_8 |= mask;
|
|
// D3 was set to GPIO high to force slave into SD mode, until 4-bit mode is set
|
|
configure_pin(d3, slot, GPIO_MODE_INPUT_OUTPUT);
|
|
} else {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
ESP_LOGD(TAG, "slot=%d width=%d", slot, width);
|
|
return ESP_OK;
|
|
}
|
|
|
|
size_t sdmmc_host_get_slot_width(int slot)
|
|
{
|
|
assert( slot == 0 || slot == 1 );
|
|
return s_slot_width[slot];
|
|
}
|
|
|
|
esp_err_t sdmmc_host_set_bus_ddr_mode(int slot, bool ddr_enabled)
|
|
{
|
|
if (!(slot == 0 || slot == 1)) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
if (s_slot_width[slot] == 8 && ddr_enabled) {
|
|
ESP_LOGW(TAG, "DDR mode with 8-bit bus width is not supported yet");
|
|
// requires reconfiguring controller clock for 2x card frequency
|
|
return ESP_ERR_NOT_SUPPORTED;
|
|
}
|
|
uint32_t mask = BIT(slot);
|
|
if (ddr_enabled) {
|
|
SDMMC.uhs.ddr |= mask;
|
|
SDMMC.emmc_ddr_reg |= mask;
|
|
} else {
|
|
SDMMC.uhs.ddr &= ~mask;
|
|
SDMMC.emmc_ddr_reg &= ~mask;
|
|
}
|
|
ESP_LOGD(TAG, "slot=%d ddr=%d", slot, ddr_enabled ? 1 : 0);
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t sdmmc_host_set_cclk_always_on(int slot, bool cclk_always_on)
|
|
{
|
|
if (!(slot == 0 || slot == 1)) {
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
if (cclk_always_on) {
|
|
SDMMC.clkena.cclk_low_power &= ~BIT(slot);
|
|
} else {
|
|
SDMMC.clkena.cclk_low_power |= BIT(slot);
|
|
}
|
|
sdmmc_host_clock_update_command(slot);
|
|
return ESP_OK;
|
|
}
|
|
|
|
static void sdmmc_host_dma_init(void)
|
|
{
|
|
SDMMC.ctrl.dma_enable = 1;
|
|
SDMMC.bmod.val = 0;
|
|
SDMMC.bmod.sw_reset = 1;
|
|
SDMMC.idinten.ni = 1;
|
|
SDMMC.idinten.ri = 1;
|
|
SDMMC.idinten.ti = 1;
|
|
}
|
|
|
|
|
|
void sdmmc_host_dma_stop(void)
|
|
{
|
|
SDMMC.ctrl.use_internal_dma = 0;
|
|
SDMMC.ctrl.dma_reset = 1;
|
|
SDMMC.bmod.fb = 0;
|
|
SDMMC.bmod.enable = 0;
|
|
}
|
|
|
|
void sdmmc_host_dma_prepare(sdmmc_desc_t* desc, size_t block_size, size_t data_size)
|
|
{
|
|
// Set size of data and DMA descriptor pointer
|
|
SDMMC.bytcnt = data_size;
|
|
SDMMC.blksiz = block_size;
|
|
SDMMC.dbaddr = desc;
|
|
|
|
// Enable everything needed to use DMA
|
|
SDMMC.ctrl.dma_enable = 1;
|
|
SDMMC.ctrl.use_internal_dma = 1;
|
|
SDMMC.bmod.enable = 1;
|
|
SDMMC.bmod.fb = 1;
|
|
sdmmc_host_dma_resume();
|
|
}
|
|
|
|
void sdmmc_host_dma_resume(void)
|
|
{
|
|
SDMMC.pldmnd = 1;
|
|
}
|
|
|
|
bool sdmmc_host_card_busy(void)
|
|
{
|
|
return SDMMC.status.data_busy == 1;
|
|
}
|
|
|
|
esp_err_t sdmmc_host_io_int_enable(int slot)
|
|
{
|
|
configure_pin(d1, slot, GPIO_MODE_INPUT_OUTPUT);
|
|
return ESP_OK;
|
|
}
|
|
|
|
esp_err_t sdmmc_host_io_int_wait(int slot, TickType_t timeout_ticks)
|
|
{
|
|
/* SDIO interrupts are negedge sensitive ones: the status bit is only set
|
|
* when first interrupt triggered.
|
|
*
|
|
* If D1 GPIO is low when entering this function, we know that interrupt
|
|
* (in SDIO sense) has occurred and we don't need to use SDMMC peripheral
|
|
* interrupt.
|
|
*/
|
|
|
|
SDMMC.intmask.sdio &= ~BIT(slot); /* Disable SDIO interrupt */
|
|
SDMMC.rintsts.sdio = BIT(slot);
|
|
if (gpio_get_level(GPIO_NUM(slot, d1)) == 0) {
|
|
return ESP_OK;
|
|
}
|
|
/* Otherwise, need to wait for an interrupt. Since D1 was high,
|
|
* SDMMC peripheral interrupt is guaranteed to trigger on negedge.
|
|
*/
|
|
xSemaphoreTake(s_io_intr_event, 0);
|
|
SDMMC.intmask.sdio |= BIT(slot); /* Re-enable SDIO interrupt */
|
|
|
|
if (xSemaphoreTake(s_io_intr_event, timeout_ticks) == pdTRUE) {
|
|
return ESP_OK;
|
|
} else {
|
|
return ESP_ERR_TIMEOUT;
|
|
}
|
|
}
|
|
|
|
/**
|
|
* @brief SDMMC interrupt handler
|
|
*
|
|
* All communication in SD protocol is driven by the master, and the hardware
|
|
* handles things like stop commands automatically.
|
|
* So the interrupt handler doesn't need to do much, we just push interrupt
|
|
* status into a queue, clear interrupt flags, and let the task currently
|
|
* doing communication figure out what to do next.
|
|
* This also applies to SDIO interrupts which are generated by the slave.
|
|
*
|
|
* Card detect interrupts pose a small issue though, because if a card is
|
|
* plugged in and out a few times, while there is no task to process
|
|
* the events, event queue can become full and some card detect events
|
|
* may be dropped. We ignore this problem for now, since the there are no other
|
|
* interesting events which can get lost due to this.
|
|
*/
|
|
static void sdmmc_isr(void* arg) {
|
|
QueueHandle_t queue = (QueueHandle_t) arg;
|
|
sdmmc_event_t event;
|
|
int higher_priority_task_awoken = pdFALSE;
|
|
|
|
uint32_t pending = SDMMC.mintsts.val & 0xFFFF;
|
|
SDMMC.rintsts.val = pending;
|
|
event.sdmmc_status = pending;
|
|
|
|
uint32_t dma_pending = SDMMC.idsts.val;
|
|
SDMMC.idsts.val = dma_pending;
|
|
event.dma_status = dma_pending & 0x1f;
|
|
|
|
if (pending != 0 || dma_pending != 0) {
|
|
xQueueSendFromISR(queue, &event, &higher_priority_task_awoken);
|
|
}
|
|
|
|
uint32_t sdio_pending = SDMMC.mintsts.sdio;
|
|
if (sdio_pending) {
|
|
// disable the interrupt (no need to clear here, this is done in sdmmc_host_io_wait_int)
|
|
SDMMC.intmask.sdio &= ~sdio_pending;
|
|
xSemaphoreGiveFromISR(s_io_intr_event, &higher_priority_task_awoken);
|
|
}
|
|
|
|
if (higher_priority_task_awoken == pdTRUE) {
|
|
portYIELD_FROM_ISR();
|
|
}
|
|
}
|
|
|
|
static esp_err_t sdmmc_host_pullup_en_internal(int slot, int width)
|
|
{
|
|
if (width > sdmmc_slot_info[slot].width) {
|
|
//in esp32 we only support 8 bit in slot 0, note this is occupied by the flash by default
|
|
return ESP_ERR_INVALID_ARG;
|
|
}
|
|
// according to the spec, the host controls the clk, we don't to pull it up here
|
|
gpio_pullup_en(GPIO_NUM(slot, cmd));
|
|
gpio_pullup_en(GPIO_NUM(slot, d0));
|
|
if (width >= 4) {
|
|
gpio_pullup_en(GPIO_NUM(slot, d1));
|
|
gpio_pullup_en(GPIO_NUM(slot, d2));
|
|
gpio_pullup_en(GPIO_NUM(slot, d3));
|
|
}
|
|
if (width == 8) {
|
|
gpio_pullup_en(GPIO_NUM(slot, d4));
|
|
gpio_pullup_en(GPIO_NUM(slot, d5));
|
|
gpio_pullup_en(GPIO_NUM(slot, d6));
|
|
gpio_pullup_en(GPIO_NUM(slot, d7));
|
|
}
|
|
return ESP_OK;
|
|
}
|